component
AD5121BCPZ10-RL7
Public Made by Adomby adom
Analog Devices Digital Potentiometers, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5121BCPZ10-RL7
Analog Devices · Digital Potentiometers · LFCSP-16(3x3)
AD5121BCPZ10-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin, logic ground reference. |
| 2 | A | passive | Terminal A of RDAC; voltage must satisfy VSS ≤ VA ≤ VDD. |
| 3 | W | passive | Wiper terminal of RDAC; voltage must satisfy VSS ≤ VW ≤ VDD. |
| 4 | B | passive | Terminal B of RDAC; voltage must satisfy VSS ≤ VB ≤ VDD. |
| 5 | VSS | power_in | Negative power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 6 | SYNC/ADDR0 | input | Programmable address ADDR0 for multiple package decoding when DIS = 1; active-low synchronization data input when DIS = 0, data is loaded into the RDAC register when SYNC returns high. |
| 7 | RESET | input | Active-low hardware reset that refreshes the RDAC registers from EEPROM; tie to VLOGIC if not used. |
| 8 | DIS | input | Digital interface select, SPI when DIS = 0 (GND) and I2C when DIS = 1 (VLOGIC); cannot be left floating. |
| 9 | VDD | power_in | Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 10 | VLOGIC | power_in | Logic power supply, 1.8 V to VDD; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 11 | SCLK/SCL | input | SPI serial clock (SCLK) or I2C serial clock (SCL); data is clocked in at logic low transition. |
| 12 | SDI/SDA | bidirectional | Serial data input/output (SDA) when DIS = 1; serial data input (SDI) when DIS = 0. |
| 13 | WP | input | Optional active-low write protect preventing changes to RDAC and EEPROM contents except when reloading EEPROM into the RDAC register; tie to VLOGIC if not used. |
| 14 | SDO/ADDR1 | bidirectional | Programmable address ADDR1 for multiple package decoding when DIS = 1; open-drain serial data output (SDO) needing an external pull-up resistor when DIS = 0. |
| 15 | INDEP | input | Linear gain setting mode at power-up, each string resistor is loaded from its associated memory location; if enabled it cannot be disabled by software. |
| 16 | LRDAC | input | Active-low load RDAC that transfers the input register contents to the RDAC register for asynchronous update; tie to VLOGIC if not used. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Integral Nonlinearity | R-INL | -1 | 0.1 | 1 | LSB | RAB = 10 kΩ, VDD ≥ 2.7 V | 3 |
| Resistor Integral Nonlinearity | R-INL | -2.5 | 1 | 2.5 | LSB | RAB = 10 kΩ, VDD < 2.7 V | 3 |
| Resistor Differential Nonlinearity | R-DNL | -0.5 | 0.1 | 0.5 | LSB | 3 | |
| Nominal Resistor Tolerance | ΔRAB/RAB | -8 | 1 | 8 | % | 3 | |
| Wiper Resistance | RW | 55 | 125 | Ω | Code = zero scale, RAB = 10 kΩ | 3 | |
| Bottom Scale or Top Scale Resistance | RBS or RTS | 40 | 80 | Ω | RAB = 10 kΩ | 3 | |
| Integral Nonlinearity | INL | -0.5 | 0.1 | 0.5 | LSB | RAB = 10 kΩ | 3 |
| Differential Nonlinearity | DNL | -0.25 | 0.1 | 0.25 | LSB | 3 | |
| Full-Scale Error | VWFSE | -1.5 | -0.1 | LSB | RAB = 10 kΩ | 3 | |
| Zero-Scale Error | VWZSE | 1 | 1.5 | LSB | RAB = 10 kΩ | 3 | |
| Maximum Continuous Current | IA, IB, IW | -6 | 6 | mA | RAB = 10 kΩ | 3 | |
| Common-Mode Leakage Current | -500 | 15 | 500 | nA | VA = VW = VB | 4 | |
| Input Current | IIN | -1 | 1 | µA | 4 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 3 mA | 4 | ||
| Output Low Voltage | VOL | 0.6 | V | ISINK = 6 mA, VLOGIC > 2.3 V | 4 | ||
| Three-State Leakage Current | -1 | 1 | µA | 4 | |||
| Single-Supply Power Range | VDD / VSS | 2.3 | 5.5 | V | VSS = GND | 4 | |
| Dual-Supply Power Range | VDD / VSS | 2.25 | 2.75 | V | printed ±2.25 to ±2.75 | 4 | |
| Logic Supply Range | VLOGIC | 1.8 | V | Single supply, VSS = GND; upper limit VDD | 4 | ||
| Logic Supply Range | VLOGIC | 2.25 | V | Dual supply, VSS < GND; upper limit VDD | 4 | ||
| Positive Supply Current | IDD | 0.7 | 5.5 | µA | VIH = VLOGIC or VIL = GND, VDD = 5.5 V | 4 | |
| Positive Supply Current | IDD | 400 | nA | VIH = VLOGIC or VIL = GND, VDD = 2.3 V | 4 | ||
| Negative Supply Current | ISS | -5.5 | -0.7 | µA | VIH = VLOGIC or VIL = GND | 4 | |
| Logic Supply Current | ILOGIC | 0.05 | 1.4 | µA | VIH = VLOGIC or VIL = GND | 4 | |
| Power Supply Rejection Ratio | PSRR | -66 | -60 | dB | ∆VDD/∆VSS = VDD ± 10%, code = full scale | 4 | |
| Resistance Temperature Coefficient | (ΔRAB/RAB)/ΔT × 10^6 | 35 | ppm/°C | Code = full scale | 3 | ||
| Voltage Divider Temperature Coefficient | (ΔVW/VW)/ΔT × 10^6 | 5 | ppm/°C | Code = half scale | 3 | ||
| Capacitance A, Capacitance B | CA, CB | 25 | pF | f = 1 MHz, measured to GND, code = half scale, RAB = 10 kΩ | 3 | ||
| Capacitance W | CW | 12 | pF | f = 1 MHz, measured to GND, code = half scale, RAB = 10 kΩ | 3 | ||
| Input Capacitance | CIN | 5 | pF | 4 | |||
| EEPROM Store Current | IDD_EEPROM_STORE | 2 | mA | VIH = VLOGIC or VIL = GND | 4 | ||
| EEPROM Read Current | IDD_EEPROM_READ | 320 | µA | VIH = VLOGIC or VIL = GND | 4 | ||
| Power Dissipation | PDISS | 3.5 | µW | VIH = VLOGIC or VIL = GND | 4 | ||
| Bandwidth | BW | 3 | MHz | -3 dB, RAB = 10 kΩ | 4 | ||
| Total Harmonic Distortion | THD | -80 | dB | VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ | 4 | ||
| Resistor Noise Density | eN_WB | 7 | nV/√Hz | Code = half scale, TA = 25°C, f = 10 kHz, RAB = 10 kΩ | 4 | ||
| VW Settling Time | tS | 2 | µs | VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band, RAB = 10 kΩ | 4 | ||
| Endurance | 1 | Mcycles | TA = 25°C | 4 | |||
| Endurance | 100 | kcycles | 4 | ||||
| Data Retention | 50 | Years | 4 | ||||
| VDD to GND | -0.3 | 7 | V | TA = 25°C | 11 | ||
| VSS to GND | -7 | 0.3 | V | TA = 25°C; printed +0.3 V to -7.0 V | 11 | ||
| VDD to VSS | 7 | V | TA = 25°C | 11 | |||
| Pulsed IA, IW, IB, frequency > 10 kHz | -6 | 6 | mA/d | RAW = 10 kΩ; d = pulse duty factor | 11 | ||
| Pulsed IA, IW, IB, frequency ≤ 10 kHz | -6 | 6 | mA/√d | RAW = 10 kΩ; d = pulse duty factor | 11 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | Includes programming of EEPROM memory | 11 | |
| Maximum Junction Temperature | TJ | 150 | °C | 11 | |||
| Storage Temperature Range | -65 | 150 | °C | 11 | |||
| Reflow Peak Temperature | 260 | °C | Time at peak 20 sec to 40 sec | 11 | |||
| Junction to Ambient Thermal Resistance | θJA | 75.4 | °C/W | 16-Lead LFCSP | 11 | ||
| Junction to Board Thermal Resistance | θJB | 33.4 | °C/W | 16-Lead LFCSP | 11 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | EPAD Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plan | 12 |
CAD (KiCad official)
- Symbol:
AD5121BCPZ10-RL7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ad5121bcpz10-rl7-etched.step/ad5121bcpz10-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5121bcpz10-rl7.step/ad5121bcpz10-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (30 pp, sha256
9e0c5cdca83084fb, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5121BCPZ10-RL7
**Analog Devices** · Digital Potentiometers · LFCSP-16(3x3)
AD5121BCPZ10-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin, logic ground reference. |
| 2 | A | passive | Terminal A of RDAC; voltage must satisfy VSS ≤ VA ≤ VDD. |
| 3 | W | passive | Wiper terminal of RDAC; voltage must satisfy VSS ≤ VW ≤ VDD. |
| 4 | B | passive | Terminal B of RDAC; voltage must satisfy VSS ≤ VB ≤ VDD. |
| 5 | VSS | power_in | Negative power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 6 | SYNC/ADDR0 | input | Programmable address ADDR0 for multiple package decoding when DIS = 1; active-low synchronization data input when DIS = 0, data is loaded into the RDAC register when SYNC returns high. |
| 7 | RESET | input | Active-low hardware reset that refreshes the RDAC registers from EEPROM; tie to VLOGIC if not used. |
| 8 | DIS | input | Digital interface select, SPI when DIS = 0 (GND) and I2C when DIS = 1 (VLOGIC); cannot be left floating. |
| 9 | VDD | power_in | Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 10 | VLOGIC | power_in | Logic power supply, 1.8 V to VDD; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 11 | SCLK/SCL | input | SPI serial clock (SCLK) or I2C serial clock (SCL); data is clocked in at logic low transition. |
| 12 | SDI/SDA | bidirectional | Serial data input/output (SDA) when DIS = 1; serial data input (SDI) when DIS = 0. |
| 13 | WP | input | Optional active-low write protect preventing changes to RDAC and EEPROM contents except when reloading EEPROM into the RDAC register; tie to VLOGIC if not used. |
| 14 | SDO/ADDR1 | bidirectional | Programmable address ADDR1 for multiple package decoding when DIS = 1; open-drain serial data output (SDO) needing an external pull-up resistor when DIS = 0. |
| 15 | INDEP | input | Linear gain setting mode at power-up, each string resistor is loaded from its associated memory location; if enabled it cannot be disabled by software. |
| 16 | LRDAC | input | Active-low load RDAC that transfers the input register contents to the RDAC register for asynchronous update; tie to VLOGIC if not used. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Integral Nonlinearity | R-INL | -1 | 0.1 | 1 | LSB | RAB = 10 kΩ, VDD ≥ 2.7 V | 3 |
| Resistor Integral Nonlinearity | R-INL | -2.5 | 1 | 2.5 | LSB | RAB = 10 kΩ, VDD < 2.7 V | 3 |
| Resistor Differential Nonlinearity | R-DNL | -0.5 | 0.1 | 0.5 | LSB | | 3 |
| Nominal Resistor Tolerance | ΔRAB/RAB | -8 | 1 | 8 | % | | 3 |
| Wiper Resistance | RW | | 55 | 125 | Ω | Code = zero scale, RAB = 10 kΩ | 3 |
| Bottom Scale or Top Scale Resistance | RBS or RTS | | 40 | 80 | Ω | RAB = 10 kΩ | 3 |
| Integral Nonlinearity | INL | -0.5 | 0.1 | 0.5 | LSB | RAB = 10 kΩ | 3 |
| Differential Nonlinearity | DNL | -0.25 | 0.1 | 0.25 | LSB | | 3 |
| Full-Scale Error | VWFSE | -1.5 | -0.1 | | LSB | RAB = 10 kΩ | 3 |
| Zero-Scale Error | VWZSE | | 1 | 1.5 | LSB | RAB = 10 kΩ | 3 |
| Maximum Continuous Current | IA, IB, IW | -6 | | 6 | mA | RAB = 10 kΩ | 3 |
| Common-Mode Leakage Current | | -500 | 15 | 500 | nA | VA = VW = VB | 4 |
| Input Current | IIN | -1 | | 1 | µA | | 4 |
| Output Low Voltage | VOL | | | 0.4 | V | ISINK = 3 mA | 4 |
| Output Low Voltage | VOL | | | 0.6 | V | ISINK = 6 mA, VLOGIC > 2.3 V | 4 |
| Three-State Leakage Current | | -1 | | 1 | µA | | 4 |
| Single-Supply Power Range | VDD / VSS | 2.3 | | 5.5 | V | VSS = GND | 4 |
| Dual-Supply Power Range | VDD / VSS | 2.25 | | 2.75 | V | printed ±2.25 to ±2.75 | 4 |
| Logic Supply Range | VLOGIC | 1.8 | | | V | Single supply, VSS = GND; upper limit VDD | 4 |
| Logic Supply Range | VLOGIC | 2.25 | | | V | Dual supply, VSS < GND; upper limit VDD | 4 |
| Positive Supply Current | IDD | | 0.7 | 5.5 | µA | VIH = VLOGIC or VIL = GND, VDD = 5.5 V | 4 |
| Positive Supply Current | IDD | | 400 | | nA | VIH = VLOGIC or VIL = GND, VDD = 2.3 V | 4 |
| Negative Supply Current | ISS | -5.5 | -0.7 | | µA | VIH = VLOGIC or VIL = GND | 4 |
| Logic Supply Current | ILOGIC | | 0.05 | 1.4 | µA | VIH = VLOGIC or VIL = GND | 4 |
| Power Supply Rejection Ratio | PSRR | | -66 | -60 | dB | ∆VDD/∆VSS = VDD ± 10%, code = full scale | 4 |
| Resistance Temperature Coefficient | (ΔRAB/RAB)/ΔT × 10^6 | | 35 | | ppm/°C | Code = full scale | 3 |
| Voltage Divider Temperature Coefficient | (ΔVW/VW)/ΔT × 10^6 | | 5 | | ppm/°C | Code = half scale | 3 |
| Capacitance A, Capacitance B | CA, CB | | 25 | | pF | f = 1 MHz, measured to GND, code = half scale, RAB = 10 kΩ | 3 |
| Capacitance W | CW | | 12 | | pF | f = 1 MHz, measured to GND, code = half scale, RAB = 10 kΩ | 3 |
| Input Capacitance | CIN | | 5 | | pF | | 4 |
| EEPROM Store Current | IDD_EEPROM_STORE | | 2 | | mA | VIH = VLOGIC or VIL = GND | 4 |
| EEPROM Read Current | IDD_EEPROM_READ | | 320 | | µA | VIH = VLOGIC or VIL = GND | 4 |
| Power Dissipation | PDISS | | 3.5 | | µW | VIH = VLOGIC or VIL = GND | 4 |
| Bandwidth | BW | | 3 | | MHz | -3 dB, RAB = 10 kΩ | 4 |
| Total Harmonic Distortion | THD | | -80 | | dB | VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ | 4 |
| Resistor Noise Density | eN_WB | | 7 | | nV/√Hz | Code = half scale, TA = 25°C, f = 10 kHz, RAB = 10 kΩ | 4 |
| VW Settling Time | tS | | 2 | | µs | VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band, RAB = 10 kΩ | 4 |
| Endurance | | | 1 | | Mcycles | TA = 25°C | 4 |
| Endurance | | | 100 | | kcycles | | 4 |
| Data Retention | | | 50 | | Years | | 4 |
| VDD to GND | | -0.3 | | 7 | V | TA = 25°C | 11 |
| VSS to GND | | -7 | | 0.3 | V | TA = 25°C; printed +0.3 V to -7.0 V | 11 |
| VDD to VSS | | | | 7 | V | TA = 25°C | 11 |
| Pulsed IA, IW, IB, frequency > 10 kHz | | -6 | | 6 | mA/d | RAW = 10 kΩ; d = pulse duty factor | 11 |
| Pulsed IA, IW, IB, frequency ≤ 10 kHz | | -6 | | 6 | mA/√d | RAW = 10 kΩ; d = pulse duty factor | 11 |
| Operating Temperature Range | TA | -40 | | 125 | °C | Includes programming of EEPROM memory | 11 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 11 |
| Storage Temperature Range | | -65 | | 150 | °C | | 11 |
| Reflow Peak Temperature | | | | 260 | °C | Time at peak 20 sec to 40 sec | 11 |
| Junction to Ambient Thermal Resistance | θJA | | 75.4 | | °C/W | 16-Lead LFCSP | 11 |
| Junction to Board Thermal Resistance | θJB | | 33.4 | | °C/W | 16-Lead LFCSP | 11 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | EPAD Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plan | 12 |
## CAD (KiCad official)
- Symbol: `AD5121BCPZ10-RL7`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `ad5121bcpz10-rl7-etched.step` / `ad5121bcpz10-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5121bcpz10-rl7.step` / `ad5121bcpz10-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5121_5141.pdf) (30 pp, sha256 `9e0c5cdca83084fb`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5121bcpz10-rl7-datasheet.pdf)