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AD5063BRMZ-REEL7

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Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD5063BRMZ-REEL7

Analog Devices · Digital To Analog Converters (DACs) · MSOP-10

AD5063BRMZ-REEL7 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIN input Serial data input to a 24-bit shift register, with data clocked in on the falling edge of the serial clock.
2 VDD power_in Power supply input that operates from 2.7 V to 5.5 V and should be decoupled to GND.
3 VREF power_in Reference voltage input with a range of 2 V to VDD − 50 mV.
4 VOUT output Analog output voltage from the DAC, ranging from 0 to VREF in unipolar operation and from −VREF to VREF in bipolar operation.
5 INV passive Connected to the internal scaling resistors of the DAC and to the external op amp inverting input in bipolar mode.
6 RFB passive Feedback resistor pin that connects to the external op amp circuit in bipolar mode.
7 AGND power_in Ground reference point for the analog circuitry.
8 DACGND power_in Ground input to the DAC.
9 SYNC input Active-low level-triggered frame synchronization input; the DAC updates after the 24th clock unless SYNC is taken high first, which aborts the write.
10 SCLK input Serial clock input, with data clocked into the shift register on the falling edge at rates of up to 30 MHz.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category ADC/DAC/Data Conversion
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL) INL -1 0.5 1 LSB −40°C to + 85°C, B grade over all codes 3
Total Unadjusted Error (TUE) TUE -800 500 800 µV 3
Differential Nonlinearity (DNL) DNL -1 0.5 1 LSB Guaranteed monotonic 3
Gain Error -0.02 0.01 0.02 % FSR TA = −40°C to +85°C 3
Zero-Code Error -0.1 0.05 0.1 mV All 0s loaded to DAC register, TA = −40°C to +85°C 3
Offset Error -0.1 0.05 0.1 mV TA = −40°C to +85°C 3
Full-Scale Error -800 500 800 µV All 1s loaded to DAC register, TA = −40°C to +85°C 3
Bipolar Zero Offset Error -16 8 16 LSB 3
Bipolar Gain Error -32 16 32 LSB 3
Output Voltage Range (unipolar) VOUT 0 V Unipolar operation; upper limit VREF 3
Output Voltage Settling Time 4 µs ¼ scale to ¾ scale code transition to ±1 LSB 3
VREF Input Range VREF 2 V Upper limit VDD − 50 mV 3
Input Current (Power-Down) -1 1 µA Zero-scale loaded 3
Input Current (Normal) -1 1 µA 3
Input Current (logic) -2 1 2 µA Total current flowing into all pins 3
Input Low Voltage VIL 0.8 V VDD = 4.5 V to 5.5 V 3
Input Low Voltage VIL 0.8 VDD VDD = 2.7 V to 3.6 V 3
Input High Voltage VIH 2 V VDD = 2.7 V to 5.5 V 3
Input High Voltage VIH 1.8 VDD VDD = 2.7 V to 3.6 V 3
Supply voltage VDD 2.7 5.5 V All digital inputs at 0 V or VDD 4
IDD (Normal Mode) IDD 0.65 0.7 mA VDD = 4.5 V to 5.5 V; VIN = VDD and VIL = GND, VDD = 5 V, VREF = 4.096 V, code = midscale 4
IDD (Normal Mode) IDD 0.5 mA VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND, VDD = 3 V 4
IDD (All Power-Down Modes) IDD 1 µA VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND 4
Digital Input Timing t1 (SCLK cycle time) t1 33 ns 5
Digital Input Timing t2 (SCLK high time) t2 5 ns 5
Digital Input Timing t3 (SCLK low time) t3 3 ns 5
Digital Input Timing t4 (SYNC to SCLK falling edge setup) t4 10 ns 5
Digital Input Timing t5 (data setup) t5 3 ns 5
Digital Input Timing t6 (data hold) t6 2 ns 5
Digital Input Timing t7 (SCLK falling edge to SYNC rising edge) t7 0 ns 5
Digital Input Timing t8 (minimum SYNC high time) t8 12 ns 5
Digital Input Timing t9 (SYNC rising edge to next SCLK fall ignore) t9 9 ns 5
VDD to GND VDD -0.3 7 V 6
Digital Input Voltage to GND -0.3 V Upper limit VDD + 0.3 V 6
VOUT to GND VOUT -0.3 V Upper limit VDD + 0.3 V 6
VREF to GND VREF -0.3 V Upper limit VDD + 0.3 V 6
INV to GND INV -0.3 V Upper limit VDD + 0.3 V 6
RFB to GND RFB -7 7 V 6
Operating Temperature Range -40 85 °C Industrial (B Version) 6
Storage Temperature Range -65 150 °C 6
Maximum Junction Temperature TJ 150 °C 6
θJA Thermal Impedance (MSOP) θJA 206 °C/W MSOP package 6
θJC Thermal Impedance (MSOP) θJC 44 °C/W MSOP package 6
Reflow Soldering Peak Temperature (Pb-free) 260 °C Printed as 260(0/−5)°C 6
Time at Peak Temperature 10 40 s Reflow soldering (Pb-Free) 6
ESD 1.5 kV 6

CAD (KiCad official)

  • Symbol: AD5063BRMZ-REEL7
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad5063brmz-reel7-etched.step / ad5063brmz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5063brmz-reel7.step / ad5063brmz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (18 pp, sha256 0b115f7cf5933f32, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF