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AD4111BCPZ

Analog Devices · Analog To Digital Converters (ADC) · LFCSP-40(6x6)

AD4111BCPZ from Analog Devices, in a LFCSP-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VINCOM	input	Voltage input common; voltage inputs are referenced to this pin when configured as single-ended, and it must be connected to analog ground.
2	VIN0	input	Voltage input 0, referenced to VINCOM in single-ended configuration or the positive input of the VIN0/VIN1 differential pair.
3	VIN1	input	Voltage input 1, referenced to VINCOM in single-ended configuration or the negative input of the VIN0/VIN1 differential pair.
4	VIN2	input	Voltage input 2, referenced to VINCOM in single-ended configuration or the positive input of the VIN2/VIN3 differential pair.
5	VIN3	input	Voltage input 3, referenced to VINCOM in single-ended configuration or the negative input of the VIN2/VIN3 differential pair.
6	REFOUT	output	Buffered output of the internal reference, 2.5 V with respect to AVSS, to be decoupled to AVSS with a 0.1 µF capacitor.
7	REGCAPA	output	Analog LDO regulator output, to be decoupled to AVSS with a 1 µF capacitor and a 0.1 µF capacitor.
8	AVSS	power_in	Negative analog supply ranging from −2.75 V to 0 V, nominally set to 0 V.
9	AVDD	power_in	Analog supply voltage ranging from 3.0 V to 5.5 V with respect to AVSS.
10	DNC	unconnected	Do not connect; nothing should be connected to this pin.
11	VBIAS−	input	Sets the bias voltage for the voltage input analog front end and must be connected to AVSS.
12	XTAL1	input	Input 1 for crystal.
13	XTAL2/CLKIO	bidirectional	Input 2 for crystal or clock input or output, with the function set by the CLOCKSEL bit in the ADCMODE register.
14	DOUT/RDY	output	Serial data output that is tristated when CS is high, and acts as a data-ready output that goes low on conversion completion when CS is low and no register is being read.
15	DIN	input	Serial data input clocked in on the SCLK rising edge, with the register address bits of the communications register selecting the target register.
16	SCLK	input	Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input.
17	CS	input	Active-low chip select; it can be hardwired low to allow 3-wire operation with SCLK, DIN and DOUT/RDY.
18	ERROR	bidirectional	Error input/output or general-purpose output selected by the ERR_EN bits in GPIOCON; in general-purpose output mode it is referenced between IOVDD and DGND.
19	SYNC	input	Synchronization input for the digital filters and analog modulators when using multiple AD4111 devices, which must be low for at least one master clock cycle to synchronize.
20	IOVDD	power_in	Digital I/O supply ranging from 2 V to 5.5 V (nominal), independent of AVDD; it must not exceed 3.6 V if AVSS is set to −2.5 V.
21	DGND	power_in	Digital ground.
22	REGCAPD	output	Digital LDO regulator output, for decoupling only, to be decoupled to DGND with a 1 µF capacitor.
23	COMPA	output	Compensation pin for VIN0, VIN2, VIN4 and VIN6, to be connected to those inputs through a 1 kΩ resistor and 680 pF capacitor when using open wire detection.
24	COMPB	output	Compensation pin for VIN1, VIN3, VIN5 and VIN7, to be connected to those inputs through a 1 kΩ resistor and 680 pF capacitor when using open wire detection.
25	GPO0	output	General-purpose digital output whose logic level is referenced to the AVDD and AVSS supplies.
26	VIN4	input	Voltage input 4, referenced to VINCOM in single-ended configuration or the positive input of the VIN4/VIN5 differential pair.
27	VIN5	input	Voltage input 5, referenced to VINCOM in single-ended configuration or the negative input of the VIN4/VIN5 differential pair.
28	VIN6	input	Voltage input 6, referenced to VINCOM in single-ended configuration or the positive input of the VIN6/VIN7 differential pair.
29	VIN7	input	Voltage input 7, referenced to VINCOM in single-ended configuration or the negative input of the VIN6/VIN7 differential pair.
30	IIN3−	input	Current input return 3, to be connected to analog ground.
31	IIN2−	input	Current input return 2, to be connected to analog ground.
32	IIN1−	input	Current input return 1, to be connected to analog ground.
33	IIN0−	input	Current input return 0, to be connected to analog ground.
34	IIN0+	input	Current input 0, paired with the IIN0− return pin.
35	IIN1+	input	Current input 1, paired with the IIN1− return pin.
36	IIN2+	input	Current input 2, paired with the IIN2− return pin.
37	IIN3+	input	Current input 3, paired with the IIN3− return pin.
38	GPO1	output	General-purpose digital output whose logic level is referenced to the AVDD and AVSS supplies.
39	REF−	input	Reference input negative terminal, which can span from AVSS to AVDD − 1 V.
40	REF+	input	Reference input positive terminal, which can span from AVDD to AVSS + 1 V.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-40(6x6)
Category	Data Acquisition
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Differential Input Voltage Range		-10		10	V	Specified performance	5
Absolute (Pin) Input Voltage		-20		20	V	AVDD ≥ 4.75 V	5
Absolute (Pin) Input Voltage		-12		12	V	AVDD = 3.0 V	5
Input Impedance		1			MΩ		5
Offset Error		-1.5		1.5	mV	25°C	5
Offset Drift		-7		7	µV/°C		5
Gain Error		-0.05		0.05	% of FS	Internal full-scale calibration, 25°C	5
Gain Drift		-1		1	ppm/°C		5
Integral Nonlinearity (INL)		-0.01		0.01	% of FSR		5
Total Unadjusted Error (TUE)		-0.06		0.06	% of FSR	25°C, internal VREF	5
Total Unadjusted Error (TUE)		-0.1		0.1	% of FSR	−40°C to +105°C, internal VREF	5
Total Unadjusted Error (TUE)		-0.08		0.08	% of FSR	−40°C to +105°C, external VREF	5
Common-Mode Rejection		120			dB	VIN = 1 V; at 50 Hz, 60 Hz; 20 Hz output data rate (postfilter), 50 Hz ± 1 Hz and 60 Hz ± 1 Hz	5
Normal Mode Rejection		71	90		dB	Internal clock, 20 SPS ODR (postfilter); 50 Hz ± 1 Hz and 60 Hz ± 1 Hz	5
Normal Mode Rejection		85	90		dB	External clock, 20 SPS ODR (postfilter); 50 Hz ± 1 Hz and 60 Hz ± 1 Hz	5
Input Current Range		-0.5		24	mA		5
Input Impedance		54	60	75	Ω		5
Offset Error		-2		2	µA		5
Gain Error		-0.02		0.02	% of FS	Factory calibrated gain, 25°C	5
Total Unadjusted Error (TUE)		-0.2		0.2	% of FSR	−40°C to +105°C, internal VREF	5
ADC Output Data Rate (ODR)		1.25		31250	SPS	One channel, see Table 6	5
No Missing Codes		24			Bits	Excluding sinc3 filter ≥ 15 kHz notch	5
Initial Accuracy (REFOUT)		-0.12		0.12	% of V	REFOUT, TA = 25°C	6
Temperature Coefficient (internal reference)			5	12	ppm/°C		6
Differential Input Range (external reference)	VREF	1	2.5		V	VREF = (REF+) − (REF−)	6
REF± Input Current		-9		9	µA/V	Buffers disabled	6
Reference Load Current	ILOAD	-10		10	mA		6
Temperature Sensor Accuracy		-2		2	°C	After user calibration at 25°C	6
Internal Clock Accuracy		-2.5		2.5	%		6
Crystal Frequency		14	16	16.384	MHz	Crystal	6
Duty Cycle (external clock)		30	50	70	%	External clock (CLKIO)	6
Leakage Current (logic inputs)		-10		10	µA		7
Output Voltage Low	VOL			0.4	V	IOVDD ≥ 4.5 V, ISINK = 2 mA	7
Leakage Current (logic output)		-10		10	µA	Floating state	7
AVDD to AVSS (Power Supply Voltage)		3		5.5	V		7
AVSS to DGND (Power Supply Voltage)		-2.75		0	V		7
IOVDD to DGND (Power Supply Voltage)		2		5.5	V		7
IOVDD to AVSS (Power Supply Voltage)				6.35	V	For AVSS < DGND	7
AVDD Current (including internal reference)			3.3	3.7	mA	Full operating mode; all outputs unloaded; digital inputs connected to IOVDD or DGND	7
IOVDD Current (internal clock)			0.6	0.8	mA	Full operating mode; internal clock; all outputs unloaded	7
AVDD to AVSS		-0.3		6.5	V		10
AVDD to DGND		-0.3		6.5	V		10
IOVDD to DGND		-0.3		6.5	V		10
IOVDD to AVSS		-0.3		7.5	V		10
AVSS to DGND		-3.25		0.3	V		10
VINx to AVSS		-50		50	V		10
Current Input Current		-50		50	mA		10
IINx+ to AVSS		-0.3			V		10
IINx− to AVSS		-0.3			V		10
Reference Input Voltage to AVSS		-0.3			V		10
Digital Input Voltage to DGND		-0.3			V		10
Digital Output Voltage to DGND		-0.3			V		10
Digital Input Current				10	mA		10
Operating Temperature Range		-40		105	°C		10
Storage Temperature Range		-65		150	°C		10
Maximum Junction Temperature				150	°C		10
Lead Soldering, Reflow Temperature				260	°C		10
Thermal Resistance, junction-to-ambient	θJA		34		°C/W	4-Layer JEDEC Board (package CP-40-15)	10

CAD (KiCad official)

Symbol: AD4111BCPZ
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: LFCSP-40(6x6) (KiCad packages3D, STEP)
3D model files: ad4111bcpz-etched.step / ad4111bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad4111bcpz.step / ad4111bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (59 pp, sha256 7b40b304b1b551b1, retrieved 2026-10-19, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF