AD2S1210WDSTZRL7

{
  "schema_version": 1,
  "type": "component",
  "slug": "ad2s1210wdstzrl7",
  "title": "AD2S1210WDSTZRL7",
  "brief": "Analog Devices ADCs/DACs - Special Purpose, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "data acquisition",
    "ad2s1210wdstzrl7",
    "factory-2.0.0",
    "extractor-text"
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  "component": {
    "mpn": "AD2S1210WDSTZRL7",
    "manufacturer": "Analog Devices",
    "package": "LQFP-48(7x7)",
    "pin_count": 48,
    "category": "Data Acquisition",
    "subcategory": "ADCs/DACs - Special Purpose",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589836614035288064",
    "parts": {
      "symbol": "ad2s1210wdstzrl7.kicad_sym",
      "footprint": "ad2s1210wdstzrl7.kicad_mod",
      "model_3d": "ad2s1210wdstzrl7-hero.glb",
      "model_3d_plain": "ad2s1210wdstzrl7-etched.glb",
      "model_3d_step": "ad2s1210wdstzrl7-etched.step",
      "model_3d_step_plain": "ad2s1210wdstzrl7.step",
      "lbr": "ad2s1210wdstzrl7.lbr"
    },
    "distributor_links": {
      "lcsc": "C459871",
      "digikey": "505-AD2S1210WDSTZRL7TR-ND",
      "mouser": "584-AD2S1210WDSTZR7"
    },
    "distributor_check": {
      "checked_at": "2026-10-20T18:40:00Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "505-AD2S1210WDSTZRL7TR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "584-AD2S1210WDSTZR7",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "RES1",
        "type": "input",
        "description": "Resolution Select 1 logic input that, together with RES0, programs the converter resolution."
      },
      {
        "number": "2",
        "name": "CS",
        "type": "input",
        "description": "Active-low chip select logic input; the device is enabled when CS is held low."
      },
      {
        "number": "3",
        "name": "RD",
        "type": "input",
        "description": "Edge-triggered logic input that, with SOE high, acts as frame sync and output enable for parallel outputs DB15 to DB0 (enabled when CS and RD are low); hold high when SOE is low."
      },
      {
        "number": "4",
        "name": "WR/FSYNC",
        "type": "input",
        "description": "Edge-triggered logic input that, with SOE high, is the input enable for DB7 to DB0 (CS and WR/FSYNC low); with SOE low it is the frame sync and enable for the serial data bus."
      },
      {
        "number": "5",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground reference; may be tied to the AGND plane and must stay within 0.3 V of AGND even on transients."
      },
      {
        "number": "6",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital supply voltage, 4.75 V to 5.25 V, within 0.3 V of AVDD even on transients."
      },
      {
        "number": "7",
        "name": "CLKIN",
        "type": "input",
        "description": "Clock input for a crystal/oscillator or single-ended clock, specified from 6.144 MHz to 10.24 MHz."
      },
      {
        "number": "8",
        "name": "XTALOUT",
        "type": "output",
        "description": "Crystal output used with CLKIN; treat as no connect when a single-ended clock source drives CLKIN."
      },
      {
        "number": "9",
        "name": "SOE",
        "type": "input",
        "description": "Serial Output Enable logic input: low selects the serial interface, high selects the parallel interface."
      },
      {
        "number": "10",
        "name": "SAMPLE",
        "type": "input",
        "description": "Sample Result logic input; a high-to-low transition transfers position and velocity data to their registers and updates the fault register."
      },
      {
        "number": "11",
        "name": "DB15/SDO",
        "type": "tri_state",
        "description": "With SOE high, DB15 three-state data output controlled by CS and RD; with SOE low, serial data output clocked out on the rising edge of SCLK."
      },
      {
        "number": "12",
        "name": "DB14/SDI",
        "type": "bidirectional",
        "description": "With SOE high, DB14 three-state data output controlled by CS and RD; with SOE low, serial data input clocked in on the falling edge of SCLK."
      },
      {
        "number": "13",
        "name": "DB13/SCLK",
        "type": "bidirectional",
        "description": "In parallel mode DB13 three-state data output controlled by CS and RD; in serial mode the serial clock input."
      },
      {
        "number": "14",
        "name": "DB12",
        "type": "tri_state",
        "description": "Data Bit 12, three-state data output controlled by CS and RD."
      },
      {
        "number": "15",
        "name": "DB11",
        "type": "tri_state",
        "description": "Data Bit 11, three-state data output controlled by CS and RD."
      },
      {
        "number": "16",
        "name": "DB10",
        "type": "tri_state",
        "description": "Data Bit 10, three-state data output controlled by CS and RD."
      },
      {
        "number": "17",
        "name": "DB9",
        "type": "tri_state",
        "description": "Data Bit 9, three-state data output controlled by CS and RD."
      },
      {
        "number": "18",
        "name": "VDRIVE",
        "type": "power_in",
        "description": "Logic power supply input setting the interface voltage, 2.3 V to 5.25 V, never exceeding AVDD or DVDD by more than 0.3 V; decouple to DGND."
      },
      {
        "number": "19",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground reference; may be tied to the AGND plane and must stay within 0.3 V of AGND even on transients."
      },
      {
        "number": "20",
        "name": "DB8",
        "type": "tri_state",
        "description": "Data Bit 8, three-state data output controlled by CS and RD."
      },
      {
        "number": "21",
        "name": "DB7",
        "type": "bidirectional",
        "description": "Data Bit 7, three-state data input/output controlled by CS, RD and WR/FSYNC."
      },
      {
        "number": "22",
        "name": "DB6",
        "type": "bidirectional",
        "description": "Data Bit 6, three-state data input/output controlled by CS, RD and WR/FSYNC."
      },
      {
        "number": "23",
        "name": "DB5",
        "type": "bidirectional",
        "description": "Data Bit 5, three-state data input/output controlled by CS, RD and WR/FSYNC."
      },
      {
        "number": "24",
        "name": "DB4",
        "type": "bidirectional",
        "description": "Data Bit 4, three-state data input/output controlled by CS, RD and WR/FSYNC."
      },
      {
        "number": "25",
        "name": "DB3",
        "type": "bidirectional",
        "description": "Data Bit 3, three-state data input/output controlled by CS, RD and WR/FSYNC."
      },
      {
        "number": "26",
        "name": "DB2",
        "type": "bidirectional",
        "description": "Data Bit 2, three-state data input/output controlled by CS, RD and WR/FSYNC."
      },
      {
        "number": "27",
        "name": "DB1",
        "type": "bidirectional",
        "description": "Data Bit 1, three-state data input/output controlled by CS, RD and WR/FSYNC."
      },
      {
        "number": "28",
        "name": "DB0",
        "type": "bidirectional",
        "description": "Data Bit 0, three-state data input/output controlled by CS, RD and WR/FSYNC."
      },
      {
        "number": "29",
        "name": "A",
        "type": "output",
        "description": "Incremental encoder emulation output A, free running and valid if the resolver input signals are valid."
      },
      {
        "number": "30",
        "name": "B",
        "type": "output",
        "description": "Incremental encoder emulation output B, free running and valid if the resolver input signals are valid."
      },
      {
        "number": "31",
        "name": "NM",
        "type": "output",
        "description": "North marker incremental encoder emulation output, free running and valid if the resolver input signals are valid."
      },
      {
        "number": "32",
        "name": "DIR",
        "type": "output",
        "description": "Direction logic output for the encoder emulation outputs, high for increasing angular rotation."
      },
      {
        "number": "33",
        "name": "RESET",
        "type": "input",
        "description": "Reset logic input; an external signal must hold it low until VDD is within the 4.75 V to 5.25 V operating range."
      },
      {
        "number": "34",
        "name": "LOT",
        "type": "output",
        "description": "Loss of Tracking logic output, indicated by a logic low and not latched."
      },
      {
        "number": "35",
        "name": "DOS",
        "type": "output",
        "description": "Degradation of Signal logic output, low when a resolver input exceeds the DOS threshold or sine/cosine amplitude mismatch occurs."
      },
      {
        "number": "36",
        "name": "A1",
        "type": "input",
        "description": "Mode Select 1 logic input that, with A0, selects the operating mode."
      },
      {
        "number": "37",
        "name": "A0",
        "type": "input",
        "description": "Mode Select 0 logic input that, with A1, selects the operating mode."
      },
      {
        "number": "38",
        "name": "EXC",
        "type": "output",
        "description": "Analog sinusoidal excitation output to the resolver, with frequency programmable via the excitation frequency register."
      },
      {
        "number": "39",
        "name": "EXC_N",
        "type": "output",
        "description": "Analog complement excitation output (EXC complement) to the resolver, with frequency programmable via the excitation frequency register."
      },
      {
        "number": "40",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground reference for analog inputs and external references; must stay within 0.3 V of DGND even on transients."
      },
      {
        "number": "41",
        "name": "SIN",
        "type": "input",
        "description": "Positive analog input of the SIN/SINLO differential pair, input range 2.3 V p-p to 4.0 V p-p."
      },
      {
        "number": "42",
        "name": "SINLO",
        "type": "input",
        "description": "Negative analog input of the SIN/SINLO differential pair, input range 2.3 V p-p to 4.0 V p-p."
      },
      {
        "number": "43",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog supply voltage, 4.75 V to 5.25 V, within 0.3 V of DVDD even on transients."
      },
      {
        "number": "44",
        "name": "COSLO",
        "type": "input",
        "description": "Negative analog input of the COS/COSLO differential pair, input range 2.3 V p-p to 4.0 V p-p."
      },
      {
        "number": "45",
        "name": "COS",
        "type": "input",
        "description": "Positive analog input of the COS/COSLO differential pair, input range 2.3 V p-p to 4.0 V p-p."
      },
      {
        "number": "46",
        "name": "REFBYP",
        "type": "passive",
        "description": "Reference bypass pin for decoupling capacitors; typical recommended values are 10 µF and 0.01 µF."
      },
      {
        "number": "47",
        "name": "REFOUT",
        "type": "output",
        "description": "Voltage reference output."
      },
      {
        "number": "48",
        "name": "RES0",
        "type": "input",
        "description": "Resolution Select 0 logic input that, together with RES1, programs the converter resolution."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
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        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Package match confirmed: the ordering guide lists AD2S1210WDSTZRL7 as 48-Lead LQFP ST-48, and the ou; Pin 8 XTALOUT is a crystal output with no defined ERC class in the datasheet; classified as passive.; Pins 11, 12 and 13 are multi-function (parallel data or serial interface). Types were chosen as tri_",
          "2/48 pins cited to the wrong page (name found elsewhere): ['22:DB6@p10', '23:DB5@p10']"
        ],
        "pages_sent": 9,
        "cost_usd": 0.0972,
        "at": "2026-10-20T18:37:58"
      },
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        "pages": 34,
        "sha256": "7e50f03b4946913f",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 48,
        "described": 48,
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        "refuses_to_fabricate": true
      }
    },
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  },
  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "LQFP-48(7x7)",
      "Category": "Data Acquisition",
      "Pins": "48"
    },
    "characteristics": {
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          "name": "SDI setup time prior to SCLK falling edge (t27)",
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        {
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