component
ACT86600QM101-T
Public Made by Adomby adom
Qorvo Power Management - Specialized, QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownACT86600QM101-T
Qorvo · Power Management - Specialized · QFN-48(6x6)
ACT86600QM101-T from Qorvo, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBOOT1 | passive | Bootstrap voltage for the Buck1 regulator; connect a 22nF or larger capacitor between VBOOT1 and SW1. |
| 2 | VIN1 | power_in | Dedicated power input to the Buck1 regulator; bypass directly to PGND1 with at least 10µF. |
| 3 | VIN1 | power_in | Dedicated power input to the Buck1 regulator; bypass directly to PGND1 with at least 10µF. |
| 4 | SW1 | power_out | Switch node for the Buck1 regulator, connected directly to the buck inductor. |
| 5 | SW1 | power_out | Switch node for the Buck1 regulator, connected directly to the buck inductor. |
| 6 | PGND1 | power_in | Power ground for the Buck1 regulator; connect directly to the exposed pad. |
| 7 | PGND2 | power_in | Power ground for the Buck2 regulator; connect directly to the exposed pad. |
| 8 | SW2 | power_out | Switch node for the Buck2 regulator, connected directly to the buck inductor. |
| 9 | SW2 | power_out | Switch node for the Buck2 regulator, connected directly to the buck inductor. |
| 10 | VIN2 | power_in | Dedicated power input to the Buck2 regulator; bypass directly to PGND2 with at least 10µF. |
| 11 | VIN2 | power_in | Dedicated power input to the Buck2 regulator; bypass directly to PGND2 with at least 10µF. |
| 12 | VBOOT2 | passive | Bootstrap voltage for the Buck2 regulator; connect a 22nF or larger capacitor between VBOOT2 and SW2. |
| 13 | VFB2 | input | Output and feedback pin for the Buck2 regulator; Kelvin connect to the buck output capacitor. |
| 14 | GPIO6 | bidirectional | Configurable GPIO6 (default function set by CMI); can be an LED current sink up to 22mA or comparator input (0.8V reference), not push-pull, 5.5V tolerant. |
| 15 | VIO | power_in | Bias supply input for the digital circuitry and GPIO pins; bypass to PGND with a 1µF ceramic capacitor. |
| 16 | GPIO7 | bidirectional | Configurable GPIO7 (default function set by CMI); can be an LED current sink up to 22mA or comparator input (0.8V reference), not push-pull, 5.5V tolerant. |
| 17 | VCC5 | power_out | 5.0V output of the PMIC that also powers the IC internally; Kelvin connect to the output capacitor with a 10µF capacitor to AGND. |
| 18 | AVIN | power_in | Analog power input to the VCC5 regulator; connect to 5.0V or the highest available supply, equal to or higher than the highest VINx. |
| 19 | SW7 | power_out | Switch node for the VCC5 generating switching regulator, connected directly to its inductor. |
| 20 | PGND7 | power_in | Power ground for the VCC5 regulator, also the AVIN ground reference. |
| 21 | GPIO1 | bidirectional | Configurable GPIO1 (default set by CMI), usable as PWREN or enable input; optional 200kΩ pullup to VIO or VCC5, cannot be an LED driver or comparator. |
| 22 | SCL | input | I2C serial clock input, open drain bus requiring a pullup resistor, up to 1000kHz. |
| 23 | SDA | bidirectional | I2C serial data pin, open drain and requires a pullup resistor. |
| 24 | AGND | power_in | Analog ground; connect to the exposed pad, routed as a separate ground plane joined to the main ground in one location. |
| 25 | VFB4 | input | Output and feedback pin for the Buck4 regulator; Kelvin connect to the buck output capacitor. |
| 26 | VBOOT4 | passive | Bootstrap voltage for the Buck4 regulator; connect a 22nF or larger capacitor between VBOOT4 and SW4. |
| 27 | VIN4 | power_in | Dedicated power input to the Buck4 regulator; bypass directly to PGND4 with at least 10µF. |
| 28 | SW4 | power_out | Switch node for the Buck4 regulator, connected directly to the buck inductor. |
| 29 | SW4 | power_out | Switch node for the Buck4 regulator, connected directly to the buck inductor. |
| 30 | PGND4 | power_in | Power ground for the Buck4 regulator; connect directly to the exposed pad. |
| 31 | PGND3 | power_in | Power ground for the Buck3 regulator; connect directly to the exposed pad. |
| 32 | SW3 | power_out | Switch node for the Buck3 regulator, connected directly to the buck inductor. |
| 33 | SW3 | power_out | Switch node for the Buck3 regulator, connected directly to the buck inductor. |
| 34 | VIN3 | power_in | Dedicated power input to the Buck3 regulator; bypass directly to PGND3 with at least 10µF. |
| 35 | VBOOT3 | passive | Bootstrap voltage for the Buck3 regulator; connect a 22nF or larger capacitor between VBOOT3 and SW3. |
| 36 | VFB3 | input | Output and feedback pin for the Buck3 regulator; Kelvin connect to the buck output capacitor. |
| 37 | GPIO4 | bidirectional | Configurable GPIO4 (default function set by CMI); standard GPIO only, not an LED driver or comparator, 5.5V tolerant. |
| 38 | GPIO5 | bidirectional | Configurable GPIO5 (default function set by CMI), typically EXT_EN; not an LED driver or comparator, 5.5V tolerant. |
| 39 | VBOOT5 | passive | Bootstrap voltage for the buck-boost; connect a capacitor between VBOOT5 and SW5. |
| 40 | VINBB | power_in | Dedicated input power pin for the buck-boost regulator; bypass directly to PGND with at least 10µF. |
| 41 | SW5 | power_out | Buck-side switch pin of the buck-boost regulator, connected to the buck-boost inductor. |
| 42 | PGND | power_in | Power ground for the buck-boost regulator. |
| 43 | SW6 | power_out | Boost-side switch pin of the buck-boost regulator, connected to the buck-boost inductor. |
| 44 | VBBST | power_out | Output of the buck-boost stage (boost followed by a step-down stage), up to 0.6A. |
| 45 | VBOOT6 | passive | Bootstrap voltage for the buck-boost; connect a capacitor between VBOOT6 and SW6. |
| 46 | GPIO3 | bidirectional | Configurable GPIO3 (default function set by CMI), typically nIRQ; not an LED driver or comparator, 5.5V tolerant. |
| 47 | GPIO2 | bidirectional | Configurable GPIO2 (default function set by CMI), typically nRESET; not an LED driver or comparator, 5.5V tolerant. |
| 48 | VFB1 | input | Output and feedback pin for the Buck1 regulator; Kelvin connect to the buck output capacitor. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Qorvo |
| Package | QFN-48(6x6) |
| Category | Power Management (PMIC) |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| All pins to GND | -0.3 | 6 | V | unless stated otherwise below | 8 | ||
| AVIN to AGND | AVIN | -0.3 | 18 | V | 8 | ||
| VCC5 to AGND | VCC5 | -0.3 | 6 | V | 8 | ||
| VIN1,2,3,4 to PGND | VIN1,2,3,4 | -0.3 | 16 | V | 8 | ||
| VFB1,2,3,4 to AGND | VFB1,2,3,4 | -0.3 | 6 | V | 8 | ||
| VINBB to PGND | VINBB | -0.3 | 16 | V | 8 | ||
| VBBST to PGND | VBBST | -0.3 | 16.5 | V | 8 | ||
| SCL, SDA to AGND | SCL, SDA | -0.3 | 6 | V | 8 | ||
| GPIO1,2,3,4,5,6,7 to AGND | GPIO1-7 | -0.3 | 6 | V | 8 | ||
| AGND, PGND | AGND, PGND | -0.3 | 0.3 | V | 8 | ||
| Operating Junction Temperature | TJ | -40 | 150 | °C | 8 | ||
| Storage Temperature | TSTG | -55 | 150 | °C | 8 | ||
| ESD Human Body Model (HBM) | VESD | 2000 | V | per JEDEC JS-001 | 8 | ||
| ESD Charged Device Model (CDM) | VESD | 500 | V | per JEDEC JS-002 | 8 | ||
| All pins to GND | 0 | 5 | V | unless stated otherwise below | 9 | ||
| AVIN to AGND | AVIN | 5 | 12 | V | 9 | ||
| VIN1,2,3,4 to PGND | VIN1,2,3,4 | 5 | 12 | V | 9 | ||
| VFB1,2,3,4 to AGND | VFB1,2,3,4 | 0.6 | 5 | V | 9 | ||
| VINBB to PGND | VINBB | 5 | 12 | V | 9 | ||
| VBBST to PGND | VBBST | 1.8 | 16 | V | 9 | ||
| GPIO1,2,3,4,5,6,7 to AGND | GPIO1-7 | 0 | 5 | V | 9 | ||
| SCL, SDA to AGND | SCL, SDA | 0 | 5 | V | 9 | ||
| Operating Junction Temperature | TJ | -10 | 105 | °C | 9 | ||
| VIO Operating Range | VIO | 1.6 | 5 | V | VIO is the reference level for GPIOs when configured as open drain outputs or as inputs | 10 | |
| VIN1,2,3,4 Input Voltage Range (AVIN, VIN1-4) | VIN | 2.7 | 14.4 | V | HV Input pin, typical pin voltage, PMIC power from VIN1. | 11 | |
| VIN1,2,3,4 Input UV Threshold, hysteresis | VIN_UV | 0.1 | 0.2 | 0.3 | V | 11 | |
| VIN1,2,3,4 Input OV Threshold, rising tolerance | VIN_OV | -4 | 4 | % | VINOV_SEL = 0 | 11 | |
| VCC5 nPOR Rising Threshold | VCC5_nPOR | 2.45 | 2.6 | 2.75 | V | VCC5>VCC5_nPOR (Rising) allows to turn on regulators. | 11 |
| VINBB Input Voltage Range | VINBB | 2.7 | 14.4 | V | 11 | ||
| AVIN, Operating Supply Current (all regulators enabled, no load, low power mode enabled) | IAVIN | 300 | 400 | µA | All Regulators Enabled but no load, buck-boost regulator is disabled. Low power mode enabled. | 12 | |
| Regulator Programmable Turn Off Delay | 0 | 15 | ms | Configurable in 1ms steps between 0ms to 15ms | 13 | ||
| nRESET Delay Timings | 20 | 100 | ms | Configurable to 20, 40, 60 or 100ms | 13 | ||
| VFB1,2 Programmable Output Voltage Range | VFB1,2 | 0.6 | 5.26 | V | Configurable in 20mV steps, (Note 1) | 14 | |
| VFB1,2 Programmable Output Voltage Range | VFB1,2 | 0.6 | 1.875 | V | Configurable in 5mV steps | 14 | |
| DC Output Voltage Accuracy | VNOM | -12.5 | 12.5 | mV | 0.6V < VFB1,2 < 1.25V, IOUT = 4A (Continuous Conduction, CCM) | 14 | |
| DC Output Voltage Accuracy | VNOM | -1 | 1 | % | VFB1,2 >= 1.25V, IOUT = 4A (Continuous Conduction, CCM) | 14 | |
| DC Output Voltage Accuracy | VNOM | -25 | 25 | mV | 0.6V < VFB1,2 < 1.25V, IOUT = 10mA (Discontinuous Conduction Mode, DCM), Low power mode disabled | 14 | |
| DC Output Voltage Accuracy | VNOM | -2 | 2 | % | VFB1,2 >= 1.25V, IOUT = 10mA (Discontinuous Conduction Mode, DCM), Low power mode disabled | 14 | |
| Power Good Threshold / POK rising | POK | 87 | 90 | 93 | %VNOM | VFB1,2 Rising, POK [] = 1 | 14 |
| Power Good Threshold / POK falling | POK | 84 | 87 | 90 | %VNOM | VFB1,2 Falling, POK [] = 0 | 14 |
| Overvoltage Fault Threshold | 107 | 113 | 117 | %VNOM | VFB1,2 Rising, relative to regulation point | 14 | |
| Emulated switching frequency accuracy | -20 | 20 | % | At the default switching frequency setting | 15 | ||
| Soft-Start Period TSS | TSS | 1000 | 1500 | µs | 5% to 95% VNOM | 15 | |
| Peak Current Limit, Cycle-by-Cycle ILIM set = 00 | ILIM | 6 | A | ILIM set = 00 | 15 | ||
| Peak Current Limit, Cycle-by-Cycle ILIM set = 11 | ILIM | 9 | A | ILIM set = 11 (Note 3) | 15 | ||
| HS FET On-Resistance | RDS(ON) | 30 | mΩ | ISW = 1A, VCC5 = 5.0V | 15 | ||
| LS FET On-Resistance | RDS(ON) | 11 | mΩ | ISW = 1A, VCC5 = 5.0V | 15 | ||
| Maximum Allowable Continuous Output Current (Buck1/2) | 6 | A | DC current output, 0.47µH, Switching frequency = 1.0MHz, VFB1,2 = 1.2V. | 14 | |||
| Maximum Allowable Continuous Output Current (Buck3/4) | 4 | A | DC current output, 0.47µH, Switching frequency = 1.0MHz, VFB3,4 = 1.2V | 16 | |||
| VBBST Programmable Output Voltage Range Buck-Boost Mode | VBBST | 9.6 | 11 | 15.95 | V | Buck-Boost Mode, Configurable in 50mV steps | 18 |
| VBBST Programmable Output Voltage Range Buck Mode | VBBST | 1 | 1.8 | 4.175 | V | Buck Mode, VBBST < VINBB*0.7 | 18 |
| Maximum Allowable Continuous Output Current (Buck-Boost) | 0.6 | A | VINBB = 12.0V, 4.7µH, Switching frequency = 1.125MHz, VBBST = 11.0V. | 18 | |||
| Iq, Supply Current (Buck Boost mode) | Iq | 620 | µA | VBBST>= 103% of regulated output voltage, Buck Boost mode, VINBB = 12V VBBST = 11.0V, No Load | 18 | ||
| Switching Frequency, CCM (HALF_FRE=1) tolerance | -10 | 10 | % | VIN = 5.0V, VBBST = 12.0V, HALF_FRE=1 (nominal 562.5 kHz) | 19 | ||
| VCC5 Operating Input Voltage Range | VCC5 | 2.7 | 18 | V | VCC5 Regulator input voltage | 24 | |
| Output Voltage accuracy (LDO mode) | VCC5 | -4 | 4 | % | PMIC internal load + 250mA External Load current applied. (At default voltage setting) | 24 | |
| Output Voltage accuracy (Buck mode) | VCC5 | -3 | 3 | % | PMIC internal load + 250mA External Load current applied. (At default voltage setting) | 24 | |
| LDO Mode (Linear Mode) current limit | 0.5 | 0.7 | 1 | A | LDO Mode (Linear Mode) | 25 | |
| Current limit cycle-by-cycle, Buck Mode | 1.6 | 2 | 2.4 | A | Cycle-by-cycle, Buck Mode | 24 | |
| SCL, SDA Input Low | VIL | 0.5 | V | VIO= 1.8V | 26 | ||
| SCL, SDA Input High | VIH | 1.25 | V | VIO= 1.8V | 26 |
CAD (KiCad official)
- Symbol:
ACT86600QM101-T - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm - 3D model: QFN-48(6x6) (KiCad packages3D, STEP)
- 3D model files:
act86600qm101-t-etched.step/act86600qm101-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);act86600qm101-t.step/act86600qm101-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Qorvo datasheet (56 pp, sha256
7c9f1186f484ee13, retrieved 2026-11-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).