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ACT108-600E
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WeEn Semiconductors TRIACs, TO-92. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ACT108-600E
WeEn Semiconductors · TRIACs · TO-92
ACT108-600E from WeEn Semiconductors, in a TO-92. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CM | passive | Common terminal (CM), listed in the pinning table as 'common' with no electrical limits given for this pin in the datasheet. |
| 2 | G | input | Gate terminal (G), listed in the pinning table as 'gate'; the datasheet specifies gate ratings only at device level (e.g. IGM 1 A, VGM 15 V, PG(AV) 0.1 W) and gives no pin-specific limits. |
| 3 | LD | passive | Load terminal (LD), listed in the pinning table as 'load'; the datasheet gives no pin-specific electrical limits for this terminal. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WeEn Semiconductors |
| Package | TO-92 |
| Category | Transistors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Repetitive peak off-state voltage | VDRM | 600 | V | 4 | |||
| RMS on-state current | IT(RMS) | 0.8 | A | full sine wave; Tlead ≤ 71 °C; Fig. 1 | 4 | ||
| Non-repetitive peak on-state current | ITSM | 13 | A | full sine wave; Tj(init) = 25 °C; tp = 20 ms; Fig. 2; Fig. 3 | 4 | ||
| Non-repetitive peak on-state current | ITSM | 14.3 | A | full sine wave; Tj(init) = 25 °C; tp = 16.7 ms | 4 | ||
| I2t for fusing | I2t | 0.32 | A²s | tp = 10 ms; SIN | 4 | ||
| Rate of rise of on-state current | dIT/dt | 100 | A/µs | IG = 20 mA | 4 | ||
| Peak gate current | IGM | 1 | A | t = 20 μs | 4 | ||
| Peak gate voltage | VGM | 15 | V | positive applied gate voltage | 4 | ||
| Average gate power | PG(AV) | 0.1 | W | over any 20 ms period | 4 | ||
| Storage temperature | Tstg | -40 | 150 | °C | 4 | ||
| Junction temperature | Tj | 125 | °C | 4 | |||
| Peak pulse voltage | VPP | 2.5 | kV | Tj = 25 °C; non-repetitive, off-state; ten pulses on each voltage polarity; 20s or more between successive pulses; Fig. 4 | 4 | ||
| Thermal resistance from junction to lead | Rth(j-lead) | 60 | K/W | full cycle with heatsink compound; Fig. 5 | 6 | ||
| Gate trigger current (LD+ G-) | IGT | 1 | 10 | mA | VD = 12 V; IT = 100 mA; LD+ G-; Tj = 25 °C; Fig. 6 | 7 | |
| Gate trigger current (LD- G-) | IGT | 1 | 10 | mA | VD = 12 V; IT = 100 mA; LD- G-; Tj = 25 °C; Fig. 6 | 7 | |
| Latching current (LD+ G-) | IL | 25 | mA | VD = 12 V; IG = 100 mA; LD+ G-; Tj = 25 °C; Fig. 7 | 7 | ||
| Latching current (LD- G-) | IL | 20 | mA | VD = 12 V; IG = 100 mA; LD- G-; Tj = 25 °C; Fig. 7 | 7 | ||
| Holding current | IH | 20 | mA | VD = 12 V; Tj = 25 °C; Fig. 7 | 7 | ||
| On-state voltage | VT | 1.3 | V | IT = 1.1 A; Tj = 25 °C; Fig. 8 | 7 | ||
| Gate trigger voltage | VGT | 0.15 | V | VD = 400 V; IT = 100 mA; Tj = 125 °C | 7 | ||
| Gate trigger voltage | VGT | 1 | V | VD = 12 V; IT = 100 mA; Tj = 25 °C | 7 | ||
| Off-state current | ID | 2 | µA | VD = 600 V; Tj = 25 °C | 7 | ||
| Off-state current | ID | 0.2 | mA | VD = 600 V; Tj = 125 °C | 7 | ||
| Clamping voltage | VCL | 650 | V | ICL = 0.1 mA; tp = 1 ms; Tj = 25 °C; Fig. 9 | 7 | ||
| Rate of rise of off-state voltage | dVD/dt | 2000 | V/µs | VDM = 402 V; Tj = 125 °C; (VDM = 67% of VDRM); exponential waveform; gate open circuit; Fig. 10 | 7 | ||
| Rate of change of commutating current | dIcom/dt | 0.5 | A/ms | VD = 400 V; Tj = 125 °C; IT(RMS) = 0.8 A; dVcom/dt = 20 V/µs; (snubberless condition); gate open circuit; Fig. 11; Fig. 12 | 7 | ||
| Thermal resistance from junction to ambient (free air) | Rth(j-a) | 150 | K/W | full cycle; printed-circuit board mounted; lead length 4 mm | 6 |
CAD (KiCad official)
- Symbol:
ACT108-600E - Footprint:
Package_TO_SOT_THT:TO-92_Inline - 3D model: TO-92 (KiCad packages3D, STEP)
- 3D model files:
act108-600e-etched.step/act108-600e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);act108-600e.step/act108-600e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: WeEn Semiconductors datasheet (13 pp, sha256
e08585708f598b18, retrieved 2026-10-29, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ACT108-600E
**WeEn Semiconductors** · TRIACs · TO-92
ACT108-600E from WeEn Semiconductors, in a TO-92. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CM | passive | Common terminal (CM), listed in the pinning table as 'common' with no electrical limits given for this pin in the datasheet. |
| 2 | G | input | Gate terminal (G), listed in the pinning table as 'gate'; the datasheet specifies gate ratings only at device level (e.g. IGM 1 A, VGM 15 V, PG(AV) 0.1 W) and gives no pin-specific limits. |
| 3 | LD | passive | Load terminal (LD), listed in the pinning table as 'load'; the datasheet gives no pin-specific electrical limits for this terminal. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WeEn Semiconductors |
| Package | TO-92 |
| Category | Transistors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Repetitive peak off-state voltage | VDRM | | | 600 | V | | 4 |
| RMS on-state current | IT(RMS) | | | 0.8 | A | full sine wave; Tlead ≤ 71 °C; Fig. 1 | 4 |
| Non-repetitive peak on-state current | ITSM | | | 13 | A | full sine wave; Tj(init) = 25 °C; tp = 20 ms; Fig. 2; Fig. 3 | 4 |
| Non-repetitive peak on-state current | ITSM | | | 14.3 | A | full sine wave; Tj(init) = 25 °C; tp = 16.7 ms | 4 |
| I2t for fusing | I2t | | | 0.32 | A²s | tp = 10 ms; SIN | 4 |
| Rate of rise of on-state current | dIT/dt | | | 100 | A/µs | IG = 20 mA | 4 |
| Peak gate current | IGM | | | 1 | A | t = 20 μs | 4 |
| Peak gate voltage | VGM | | | 15 | V | positive applied gate voltage | 4 |
| Average gate power | PG(AV) | | | 0.1 | W | over any 20 ms period | 4 |
| Storage temperature | Tstg | -40 | | 150 | °C | | 4 |
| Junction temperature | Tj | | | 125 | °C | | 4 |
| Peak pulse voltage | VPP | | | 2.5 | kV | Tj = 25 °C; non-repetitive, off-state; ten pulses on each voltage polarity; 20s or more between successive pulses; Fig. 4 | 4 |
| Thermal resistance from junction to lead | Rth(j-lead) | | | 60 | K/W | full cycle with heatsink compound; Fig. 5 | 6 |
| Gate trigger current (LD+ G-) | IGT | 1 | | 10 | mA | VD = 12 V; IT = 100 mA; LD+ G-; Tj = 25 °C; Fig. 6 | 7 |
| Gate trigger current (LD- G-) | IGT | 1 | | 10 | mA | VD = 12 V; IT = 100 mA; LD- G-; Tj = 25 °C; Fig. 6 | 7 |
| Latching current (LD+ G-) | IL | | | 25 | mA | VD = 12 V; IG = 100 mA; LD+ G-; Tj = 25 °C; Fig. 7 | 7 |
| Latching current (LD- G-) | IL | | | 20 | mA | VD = 12 V; IG = 100 mA; LD- G-; Tj = 25 °C; Fig. 7 | 7 |
| Holding current | IH | | | 20 | mA | VD = 12 V; Tj = 25 °C; Fig. 7 | 7 |
| On-state voltage | VT | | | 1.3 | V | IT = 1.1 A; Tj = 25 °C; Fig. 8 | 7 |
| Gate trigger voltage | VGT | 0.15 | | | V | VD = 400 V; IT = 100 mA; Tj = 125 °C | 7 |
| Gate trigger voltage | VGT | | | 1 | V | VD = 12 V; IT = 100 mA; Tj = 25 °C | 7 |
| Off-state current | ID | | | 2 | µA | VD = 600 V; Tj = 25 °C | 7 |
| Off-state current | ID | | | 0.2 | mA | VD = 600 V; Tj = 125 °C | 7 |
| Clamping voltage | VCL | 650 | | | V | ICL = 0.1 mA; tp = 1 ms; Tj = 25 °C; Fig. 9 | 7 |
| Rate of rise of off-state voltage | dVD/dt | 2000 | | | V/µs | VDM = 402 V; Tj = 125 °C; (VDM = 67% of VDRM); exponential waveform; gate open circuit; Fig. 10 | 7 |
| Rate of change of commutating current | dIcom/dt | 0.5 | | | A/ms | VD = 400 V; Tj = 125 °C; IT(RMS) = 0.8 A; dVcom/dt = 20 V/µs; (snubberless condition); gate open circuit; Fig. 11; Fig. 12 | 7 |
| Thermal resistance from junction to ambient (free air) | Rth(j-a) | | 150 | | K/W | full cycle; printed-circuit board mounted; lead length 4 mm | 6 |
## CAD (KiCad official)
- Symbol: `ACT108-600E`
- Footprint: `Package_TO_SOT_THT:TO-92_Inline`
- 3D model: TO-92 (KiCad packages3D, STEP)
- 3D model files: `act108-600e-etched.step` / `act108-600e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `act108-600e.step` / `act108-600e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [WeEn Semiconductors datasheet](docs/act108-600e-datasheet.pdf) (13 pp, sha256 `e08585708f598b18`, retrieved 2026-10-29, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/act108-600e-datasheet.pdf)