component
ACT102H-600D
Public Made by Adomby adom
WeEn Semiconductors TRIACs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ACT102H-600D
WeEn Semiconductors · TRIACs · SO-8
ACT102H-600D from WeEn Semiconductors, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | n.c. | unconnected | Not connected; the datasheet specifies no function for this pin. |
| 2 | LD | passive | Load terminal of the AC thyristor power switch, with full cycle AC conduction. |
| 3 | n.c. | unconnected | Not connected; the datasheet specifies no function for this pin. |
| 4 | n.c. | unconnected | Not connected; the datasheet specifies no function for this pin. |
| 5 | G | input | Gate terminal for negative gate triggering; the remote gate separates the gate driver from the effects of the load current. |
| 6 | CM | passive | Common terminal of the switch, shared with pin 7. |
| 7 | CM | passive | Common terminal of the switch, shared with pin 6. |
| 8 | n.c. | unconnected | Not connected; the datasheet specifies no function for this pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WeEn Semiconductors |
| Package | SO-8 |
| Category | Transistors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Repetitive peak off-state voltage | VDRM | 600 | V | 3 | |||
| RMS on-state current | IT(RMS) | 0.2 | A | full sine wave; Tamb ≤ 100 °C; Fig. 1; Fig. 2 | 3 | ||
| Non-repetitive peak on-state current | ITSM | 8.8 | A | full sine wave; Tj(init) = 25 °C; tp = 16.7 ms | 3 | ||
| Non-repetitive peak on-state current | ITSM | 8 | A | full sine wave; Tj(init) = 25 °C; tp = 20 ms; Fig. 3; Fig. 4 | 3 | ||
| I2t for fusing | I2t | 0.31 | A²s | tp = 10 ms; SIN | 3 | ||
| Rate of rise of on-state current | dIT/dt | 50 | A/µs | IG = 10 mA | 3 | ||
| Peak gate current | IGM | 1 | A | t = 20 μs | 3 | ||
| Peak gate power | PGM | 2 | W | 3 | |||
| Average gate power | PG(AV) | 0.1 | W | over any 20 ms period | 3 | ||
| Storage temperature | Tstg | -40 | 150 | °C | 3 | ||
| Junction temperature | Tj | 125 | °C | 3 | |||
| Peak pulse voltage | VPP | 2 | kV | Tj = 25 °C; non-repetitive, off-state; Fig. 5 | 3 | ||
| Thermal resistance from junction to ambient | Rth(j-a) | 150 | K/W | full cycle; Fig. 6 | 6 | ||
| Gate trigger current (LD+ G-) | IGT | 0.5 | 5 | mA | VD = 12 V; IT = 100 mA; LD+ G-; Tj = 25 °C; Fig. 7 | 7 | |
| Gate trigger current (LD- G-) | IGT | 0.5 | 5 | mA | VD = 12 V; IT = 100 mA; LD- G-; Tj = 25 °C; Fig. 7 | 7 | |
| Latching current (LD+ G-) | IL | 25 | mA | VD = 12 V; IG = 100 mA; LD+ G-; Tj = 25 °C; Fig. 8 | 7 | ||
| Latching current (LD- G-) | IL | 25 | mA | VD = 12 V; IG = 100 mA; LD- G-; Tj = 25 °C; Fig. 8 | 7 | ||
| Holding current | IH | 20 | mA | VD = 12 V; Tj = 25 °C; Fig. 9 | 7 | ||
| On-state voltage | VT | 1.2 | V | IT = 0.3 A; Tj = 25 °C; Fig. 10 | 7 | ||
| Gate trigger voltage | VGT | 0.15 | V | VD = 400 V; IT = 100 mA; Tj = 125 °C | 7 | ||
| Gate trigger voltage | 0.9 | V | VD = 12 V; IT = 100 mA; Tj = 25 °C | 7 | |||
| Off-state current | ID | 2 | µA | VD = 600 V; Tj = 25 °C | 7 | ||
| Off-state current | ID | 0.2 | mA | VD = 600 V; Tj = 125 °C | 7 | ||
| Clamping voltage | VCL | 650 | V | ICL = 0.1 mA; tp = 1 ms; Tj = 125 °C | 7 | ||
| Rate of rise of off-state voltage | dVD/dt | 300 | V/µs | VDM = 402 V; Tj = 125 °C; (VDM = 67% of VDRM); exponential waveform; gate open circuit; Fig. 11 | 7 | ||
| Rate of change of commutating current | dIcom/dt | 0.15 | A/ms | VD = 400 V; Tj = 125 °C; IT(RMS) = 1 A; dVcom/dt = 15 V/µs; gate open circuit; Fig. 12; Fig. 13 | 7 |
CAD (KiCad official)
- Symbol:
ACT102H-600D - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
act102h-600d-etched.step/act102h-600d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);act102h-600d.step/act102h-600d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: WeEn Semiconductors datasheet (13 pp, sha256
b8c609641be71038, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ACT102H-600D
**WeEn Semiconductors** · TRIACs · SO-8
ACT102H-600D from WeEn Semiconductors, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | n.c. | unconnected | Not connected; the datasheet specifies no function for this pin. |
| 2 | LD | passive | Load terminal of the AC thyristor power switch, with full cycle AC conduction. |
| 3 | n.c. | unconnected | Not connected; the datasheet specifies no function for this pin. |
| 4 | n.c. | unconnected | Not connected; the datasheet specifies no function for this pin. |
| 5 | G | input | Gate terminal for negative gate triggering; the remote gate separates the gate driver from the effects of the load current. |
| 6 | CM | passive | Common terminal of the switch, shared with pin 7. |
| 7 | CM | passive | Common terminal of the switch, shared with pin 6. |
| 8 | n.c. | unconnected | Not connected; the datasheet specifies no function for this pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WeEn Semiconductors |
| Package | SO-8 |
| Category | Transistors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Repetitive peak off-state voltage | VDRM | | | 600 | V | | 3 |
| RMS on-state current | IT(RMS) | | | 0.2 | A | full sine wave; Tamb ≤ 100 °C; Fig. 1; Fig. 2 | 3 |
| Non-repetitive peak on-state current | ITSM | | | 8.8 | A | full sine wave; Tj(init) = 25 °C; tp = 16.7 ms | 3 |
| Non-repetitive peak on-state current | ITSM | | | 8 | A | full sine wave; Tj(init) = 25 °C; tp = 20 ms; Fig. 3; Fig. 4 | 3 |
| I2t for fusing | I2t | | | 0.31 | A²s | tp = 10 ms; SIN | 3 |
| Rate of rise of on-state current | dIT/dt | | | 50 | A/µs | IG = 10 mA | 3 |
| Peak gate current | IGM | | | 1 | A | t = 20 μs | 3 |
| Peak gate power | PGM | | | 2 | W | | 3 |
| Average gate power | PG(AV) | | | 0.1 | W | over any 20 ms period | 3 |
| Storage temperature | Tstg | -40 | | 150 | °C | | 3 |
| Junction temperature | Tj | | | 125 | °C | | 3 |
| Peak pulse voltage | VPP | | | 2 | kV | Tj = 25 °C; non-repetitive, off-state; Fig. 5 | 3 |
| Thermal resistance from junction to ambient | Rth(j-a) | | 150 | | K/W | full cycle; Fig. 6 | 6 |
| Gate trigger current (LD+ G-) | IGT | 0.5 | | 5 | mA | VD = 12 V; IT = 100 mA; LD+ G-; Tj = 25 °C; Fig. 7 | 7 |
| Gate trigger current (LD- G-) | IGT | 0.5 | | 5 | mA | VD = 12 V; IT = 100 mA; LD- G-; Tj = 25 °C; Fig. 7 | 7 |
| Latching current (LD+ G-) | IL | | | 25 | mA | VD = 12 V; IG = 100 mA; LD+ G-; Tj = 25 °C; Fig. 8 | 7 |
| Latching current (LD- G-) | IL | | | 25 | mA | VD = 12 V; IG = 100 mA; LD- G-; Tj = 25 °C; Fig. 8 | 7 |
| Holding current | IH | | | 20 | mA | VD = 12 V; Tj = 25 °C; Fig. 9 | 7 |
| On-state voltage | VT | | | 1.2 | V | IT = 0.3 A; Tj = 25 °C; Fig. 10 | 7 |
| Gate trigger voltage | VGT | 0.15 | | | V | VD = 400 V; IT = 100 mA; Tj = 125 °C | 7 |
| Gate trigger voltage | | | | 0.9 | V | VD = 12 V; IT = 100 mA; Tj = 25 °C | 7 |
| Off-state current | ID | | | 2 | µA | VD = 600 V; Tj = 25 °C | 7 |
| Off-state current | ID | | | 0.2 | mA | VD = 600 V; Tj = 125 °C | 7 |
| Clamping voltage | VCL | 650 | | | V | ICL = 0.1 mA; tp = 1 ms; Tj = 125 °C | 7 |
| Rate of rise of off-state voltage | dVD/dt | 300 | | | V/µs | VDM = 402 V; Tj = 125 °C; (VDM = 67% of VDRM); exponential waveform; gate open circuit; Fig. 11 | 7 |
| Rate of change of commutating current | dIcom/dt | 0.15 | | | A/ms | VD = 400 V; Tj = 125 °C; IT(RMS) = 1 A; dVcom/dt = 15 V/µs; gate open circuit; Fig. 12; Fig. 13 | 7 |
## CAD (KiCad official)
- Symbol: `ACT102H-600D`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `act102h-600d-etched.step` / `act102h-600d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `act102h-600d.step` / `act102h-600d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [WeEn Semiconductors datasheet](docs/act102h-600d-datasheet.pdf) (13 pp, sha256 `b8c609641be71038`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/act102h-600d-datasheet.pdf)