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ACSL-6210-50RE

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Broadcom/AVAGO Optocouplers - Logic Output, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentoptocoupler-led-digital tube-photoelectric deviceacsl-6210-50refactory-2.0.0extractor-text

Verified ACSL-6210-50RE

by Ray · last 4 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

4 Nov 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ACSL-6210-50RE · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C6795963, digikey 516-2915-2-ND, mouser 630-ACSL-6210-50RE
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-0v98ezvg/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.7)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ acsl-6210-50re.kicad_sym✓ acsl-6210-50re.kicad_mod✓ acsl-6210-50re.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers acsl-6210-50re: viewers · Ray 2d ago
acsl-6210-50re-etched.glb Publish 0.1.0 · Ray 2d ago
acsl-6210-50re-etched.step acsl-6210-50re: factory component page (tier=lcsc) · Ray 2d ago
acsl-6210-50re-hero.glb acsl-6210-50re: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
acsl-6210-50re-hero.overlay.json Publish 0.1.0 · Ray 2d ago
acsl-6210-50re.glb Publish 0.1.0 · Ray 2d ago
acsl-6210-50re.kicad_mod Publish 0.1.0 · Ray 2d ago
acsl-6210-50re.kicad_sym Publish 0.1.0 · Ray 2d ago
acsl-6210-50re.lbr Publish 0.1.0 · Ray 2d ago
acsl-6210-50re.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier lcsc, 8 pins · Ray 2d ago

ACSL-6210-50RE

Broadcom/AVAGO · Optocouplers - Logic Output · SOIC-8

ACSL-6210-50RE from Broadcom/AVAGO, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND1/CATHODE2 power_in Side-1 ground, shared internally with the cathode of LED 2; connect a 0.1-µF bypass capacitor between VDD1 and GND1.
2 VO1 output Channel 1 open-collector Schottky-clamped output (inverting, LED ON gives low), with 330 Ω to 4 kΩ pull-up resistor recommended and 7 V absolute maximum.
3 VDD1 power_in Power supply 1 for the channel 1 output detector, 3.0 V to 5.5 V recommended (7 V absolute maximum), bypassed with 0.1 µF to GND1.
4 ANODE2 input LED anode of channel 2, driven with 7 mA to 15 mA forward current for the ON state (15 mA average maximum).
5 GND2/CATHODE1 power_in Side-2 ground, shared internally with the cathode of LED 1; connect a 0.1-µF bypass capacitor between VDD2 and GND2.
6 VO2 output Channel 2 open-collector Schottky-clamped output (inverting, LED ON gives low), with 330 Ω to 4 kΩ pull-up resistor recommended and 7 V absolute maximum.
7 VDD2 power_in Power supply 2 for the channel 2 output detector, 3.0 V to 5.5 V recommended (7 V absolute maximum), bypassed with 0.1 µF to GND2.
8 ANODE1 input LED anode of channel 1, driven with 7 mA to 15 mA forward current for the ON state (15 mA average maximum).

Key specifications

Parameter Value
Manufacturer Broadcom/AVAGO
Package SOIC-8
Category Optocoupler/LED/Digital Tube/Photoelectric Device
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature Ts -55 125 °C 10
Supply Voltage (1 minute maximum) VDD1, VDD2 7 V 1 minute maximum 10
Reverse Input Voltage (per channel) VR 5 V Per channel 10
Output Voltage (per channel) VO 7 V Per channel 10
Average Forward Input Current (per channel) IF 15 mA Average, per channel; peaking up to 50 mA for 50 ns max pulse width allowed if average not exceeded 10
Output Current (per channel) IO 50 mA Per channel 10
Input Power Dissipation (per channel) PI 27 mW Per channel; SO8 derate 1.57 mW/°C linearly above +95°C free-air 10
Output Power Dissipation (per channel) PO 65 mW Per channel 10
Operating Temperature TA -40 100 °C 10
Input Current, Low Level IFL 0 250 µA Off condition guaranteed when VFL ≤ 0.8V 10
Input Current, High Level IFH 7 15 mA 10
Supply Voltage VDD1, VDD2 3 5.5 V 10
Fan Out N 5 TTL Loads At RL = 1 kΩ 10
Output Pull-up Resistor RL 330 Ω 10
Input-Output Momentary Withstand Voltage (SO8) VISO 2500 Vrms RH 50%, t = 1 min. 13
Input Threshold Current ITH 2.7 7 mA 3.0V ≤ VDD ≤ 3.6V table: IOL(Sinking) = 13 mA, VO = 0.6V 11
High Level Output Current IOH 4.7 100 µA 3.0V ≤ VDD ≤ 3.6V table: IF = 250 µA, VO = 3.3V 11
Low Level Output Voltage VOL 0.36 0.68 V 3.0V ≤ VDD ≤ 3.6V table: IOL(Sinking) = 13 mA, IF = 7mA 11
High Level Supply Current (per channel) IDDH 3.2 5 mA 3.0V ≤ VDD ≤ 3.6V table: IF = 0 mA 11
Low Level Supply Current (per channel) IDDL 4.6 7.5 mA 3.0V ≤ VDD ≤ 3.6V table: IF = 10 mA 11
Input Forward Voltage VF 1.25 1.52 1.8 V 3.0V ≤ VDD ≤ 3.6V table: IF = 10 mA, TA = 25°C 11
Input Reverse Breakdown Voltage BVR 5 V 3.0V ≤ VDD ≤ 3.6V table: IR = 10 µA 11
Maximum Data Rate 10 15 MBd 3.0V ≤ VDD ≤ 3.6V table: RL = 350Ω, CL = 15 pF 11
Pulse Width tPW 100 ns 3.0V ≤ VDD ≤ 3.6V table: RL = 350Ω, CL = 15 pF 11
Propagation Delay Time to Logic High Output Level tPLH 52 100 ns 3.0V ≤ VDD ≤ 3.6V table: RL = 350Ω, CL = 15 pF 11
Propagation Delay Time to Logic Low Output Level tPHL 44 100 ns 3.0V ≤ VDD ≤ 3.6V table: RL = 350Ω, CL = 15 pF 11
Pulse Width Distortion /PWD/ 8 35 ns 3.0V ≤ VDD ≤ 3.6V table: RL = 350Ω, CL = 15 pF 11
Propagation Delay Skew tPSK 40 ns 3.0V ≤ VDD ≤ 3.6V table: RL = 350Ω, CL = 15 pF 11
Logic High Common Mode Transient Immunity /CMH/ 10 kV/µs 3.0V ≤ VDD ≤ 3.6V table: Vcm = 1000V, IF = 0 mA, VO = 2.0V, RL = 350Ω, TA = 25°C 11
Logic Low Common Mode Transient Immunity /CML/ 10 kV/µs 3.0V ≤ VDD ≤ 3.6V table: Vcm = 1000V, IF = 8 mA, VO = 0.8V, RL = 350Ω, TA = 25°C 11
Input Threshold Current ITH 2.7 7 mA 4.5V ≤ VDD ≤ 5.5V table: IOL(Sinking) = 13 mA, VO = 0.6V 12
High Level Output Current IOH 3.8 100 µA 4.5V ≤ VDD ≤ 5.5V table: IF = 250 µA, VO = 5.5V 12
Low Level Output Voltage VOL 0.36 0.6 V 4.5V ≤ VDD ≤ 5.5V table: IOL(Sinking) = 13 mA, IF = 7 mA 12
High Level Supply Current (per channel) IDDH 4.3 7.5 mA 4.5V ≤ VDD ≤ 5.5V table: IF = 0 mA 12
Low Level Supply Current (per channel) IDDL 5.8 10.5 mA 4.5V ≤ VDD ≤ 5.5V table: IF = 10 mA 12
Input Forward Voltage VF 1.25 1.52 1.8 V 4.5V ≤ VDD ≤ 5.5V table: IF = 10 mA, TA = 25°C 12
Input Reverse Breakdown Voltage BVR 5 V 4.5V ≤ VDD ≤ 5.5V table: IR = 10 µA 12
Maximum Data Rate 10 15 MBd 4.5V ≤ VDD ≤ 5.5V table: RL = 350Ω, CL = 15 pF 12
Pulse Width tPW 100 ns 4.5V ≤ VDD ≤ 5.5V table: RL = 350Ω, CL = 15 pF 12
Propagation Delay Time to Logic High Output Level tPLH 46 100 ns 4.5V ≤ VDD ≤ 5.5V table: RL = 350Ω, CL = 15 pF 12
Propagation Delay Time to Logic Low Output Level tPHL 43 100 ns 4.5V ≤ VDD ≤ 5.5V table: RL = 350Ω, CL = 15 pF 12
Pulse Width Distortion /PWD/ 5 35 ns 4.5V ≤ VDD ≤ 5.5V table: RL = 350Ω, CL = 15 pF 12
Propagation Delay Skew tPSK 40 ns 4.5V ≤ VDD ≤ 5.5V table: RL = 350Ω, CL = 15 pF 12
Logic High Common Mode Transient Immunity /CMH/ 10 kV/µs 4.5V ≤ VDD ≤ 5.5V table: Vcm = 1000V, IF = 0 mA, VO = 2.0V, RL = 350Ω, TA = 25°C 12
Logic Low Common Mode Transient Immunity /CML/ 10 kV/µs 4.5V ≤ VDD ≤ 5.5V table: Vcm = 1000V, IF = 8 mA, VO = 0.8V, RL = 350Ω, TA = 25°C 12

CAD (KiCad official)

  • Symbol: ACSL-6210-50RE
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: acsl-6210-50re-etched.step / acsl-6210-50re-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); acsl-6210-50re.step / acsl-6210-50re.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Broadcom/AVAGO datasheet (20 pp, sha256 893adb307f5ec748, retrieved 2026-11-04, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF