component
ACS725LLCTR-50AB-T
Public Made by Adomby adom
Allegro MicroSystems LLC Current Sensors, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownACS725LLCTR-50AB-T
Allegro MicroSystems LLC · Current Sensors · SOIC-8
ACS725LLCTR-50AB-T from Allegro MicroSystems LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for the current being sensed, fused internally; pins 1 and 2 are the primary conductor input and connect to pins 3 and 4 through the 1.2 mΩ typical conductor path. |
| 2 | IP+ | passive | Terminal for the current being sensed, fused internally; pins 1 and 2 are the primary conductor input and connect to pins 3 and 4 through the 1.2 mΩ typical conductor path. |
| 3 | IP- | passive | Terminal for the current being sensed, fused internally; pins 3 and 4 are the primary conductor output and are the return end of the sensed path from pins 1 and 2. |
| 4 | IP- | passive | Terminal for the current being sensed, fused internally; pins 3 and 4 are the primary conductor output and are the return end of the sensed path from pins 1 and 2. |
| 5 | GND | power_in | Signal ground terminal; the datasheet states the sensor leads (pins 5 through 8) are electrically isolated from the primary terminals. |
| 6 | FILTER | passive | Terminal for an external capacitor that sets the output bandwidth, forming an RC circuit with the internal 1.8 kΩ filter resistance (CF = 1 nF in the typical application). |
| 7 | VIOUT | output | Analog output signal that changes proportionally with the bidirectional AC or DC primary current, with a positive slope for increasing current from pins 1 and 2 to pins 3 and 4; the output load must be at least 4.7 kΩ and at most 10 nF to GND. |
| 8 | VCC | power_in | Device power supply terminal; the supply is specified at 3.0 to 3.6 V (3.3 V typical) with an absolute maximum of 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | SOIC-8 |
| Category | Magnetic Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Current Sensing Range | IPR | -50 | 50 | A | 11 | ||
| Supply Voltage | VCC | 3 | 3.3 | 3.6 | V | 5 | |
| Supply Current | ICC | 10 | 14 | mA | VCC = 3.3 V, output open | 5 | |
| Output Capacitance Load | CL | 10 | nF | VIOUT to GND | 5 | ||
| Output Resistive Load | RL | 4.7 | kΩ | VIOUT to GND | 5 | ||
| Nonlinearity | ELIN | -1.5 | 1.5 | % | Through full range of IP | 5 | |
| Total Output Error | ETOT | -2 | 1 | 2 | % | IP = IPR(max); TA = 25°C to 150°C; typ is ±3σ | 11 |
| Total Output Error | ETOT | -6 | 4 | 6 | % | IP = IPR(max); TA = -40°C to 25°C; typ is ±3σ | 11 |
| Sensitivity Error | Esens | -1.5 | 1 | 1.5 | % | IP = IPR(max); TA = 25°C to 150°C; typ is ±3σ | 11 |
| Sensitivity Error | Esens | -5.5 | 4 | 5.5 | % | IP = IPR(max); TA = -40°C to 25°C; typ is ±3σ | 11 |
| Offset Voltage | VOE | -10 | 3 | 10 | mV | IP = 0 A; TA = 25°C to 150°C; typ is ±3σ | 11 |
| Offset Voltage | VOE | -30 | 5 | 30 | mV | IP = 0 A; TA = -40°C to 25°C; typ is ±3σ | 11 |
| Sensitivity Error Lifetime Drift | Esens_drift | -3 | 1 | 3 | % | 11 | |
| Total Output Error Lifetime Drift | Etot_drift | -3 | 1 | 3 | % | 11 | |
| Supply Voltage (absolute maximum) | VCC | 6 | V | 3 | |||
| Reverse Supply Voltage | VRCC | -0.1 | V | 3 | |||
| Reverse Output Voltage | VRIOUT | -0.1 | V | 3 | |||
| Operating Ambient Temperature Range L | TA | -40 | 150 | °C | Range L | 3 | |
| Junction Temperature | TJ(max) | 165 | °C | 3 | |||
| Storage Temperature | Tstg | -65 | 165 | °C | 3 | ||
| Package Thermal Resistance (Junction to Ambient) | RθJA | 23 | °C/W | Allegro 85-0140 evaluation board, 800 mm² 4 oz copper each side | 3 | ||
| Package Thermal Resistance (Junction to Lead) | RθJL | 5 | °C/W | Allegro ASEK725 evaluation board | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | through the primary copper conduction path (from pins 1 and | 1 |
CAD (KiCad official)
- Symbol:
ACS725LLCTR-50AB-T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
acs725llctr-50ab-t-etched.step/acs725llctr-50ab-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs725llctr-50ab-t.step/acs725llctr-50ab-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (19 pp, sha256
9bda084881510f93, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).