component
ACS725LLCTR-20AB-T
Public Made by Adomby adom
Allegro MicroSystems LLC Current Sensors, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
acs725llctr-20ab-t: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
2a99c98
1mo ago
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{
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"type": "component",
"slug": "acs725llctr-20ab-t",
"title": "ACS725LLCTR-20AB-T",
"brief": "Allegro MicroSystems LLC Current Sensors, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
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"manufacturer": "Allegro MicroSystems LLC",
"package": "SOP-8",
"pin_count": 8,
"category": "Sensor",
"subcategory": "Current Sensors",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/7b53fbc820ba1e0027fc317be68669c1.pdf",
"parts": {
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"lbr": "acs725llctr-20ab-t.lbr"
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"distributor_links": {},
"pins": [
{
"number": "1",
"name": "IP+",
"type": "passive",
"description": "Primary current input terminal (positive side of the sensed current path). Pins 1 and 2 are tied together internally to the copper conduction path (1.2 mΩ typical) that carries the primary current being sensed. Fused internally."
},
{
"number": "2",
"name": "IP+",
"type": "passive",
"description": "Primary current input terminal (positive side of the sensed current path). Pins 1 and 2 are tied together internally to the copper conduction path (1.2 mΩ typical). Fused internally."
},
{
"number": "3",
"name": "IP-",
"type": "passive",
"description": "Primary current return terminal (negative side of the sensed current path). Pins 3 and 4 are tied together internally to the copper conduction path (1.2 mΩ typical). Fused internally."
},
{
"number": "4",
"name": "IP-",
"type": "passive",
"description": "Primary current return terminal (negative side of the sensed current path). Pins 3 and 4 are tied together internally to the copper conduction path (1.2 mΩ typical). Fused internally."
},
{
"number": "5",
"name": "GND",
"type": "power_in",
"description": "Signal ground terminal. Reference for VCC, VIOUT, and the FILTER capacitor."
},
{
"number": "6",
"name": "FILTER",
"type": "passive",
"description": "Terminal for an external capacitor (C_F) that sets the output bandwidth. Forms an internal RC low-pass filter with R_F(int) = 1.8 kΩ typical; a 1 nF cap is used for the default 120 kHz bandwidth, larger caps reduce bandwidth for better noise performance."
},
{
"number": "7",
"name": "VIOUT",
"type": "output",
"description": "Analog output voltage proportional to the sensed primary current I_P. Ratiometric to VCC with a quiescent output at VCC/2 and 66 mV/A sensitivity (typ) for the -20AB variant (±20 A range). Drives a resistive load ≥4.7 kΩ and capacitive load ≤10 nF."
},
{
"number": "8",
"name": "VCC",
"type": "power_in",
"description": "Device power supply terminal. 3.3 V single-supply operation (3.0 V min, 3.6 V max); I_CC = 10 mA typ, 14 mA max. Bypass with 0.1 µF C_BYPASS to GND."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/7b53fbc820ba1e0027fc317be68669c1.pdf",
"pages": 24,
"sha256": "2c79a87c5a09ef07",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "acs725llctr-20ab-t.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
4.9,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "acs725llctr-20ab-t-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
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"seat": "z = 0",
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"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "aeef5c4aeecf819afba0da1155ba5bb42377139dd20babea8c4efc4373749358",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Allegro MicroSystems LLC",
"Package": "SOP-8",
"Category": "Sensor",
"Pins": "8"
}
},
"sections": [
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"discovery_triggers": [
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"discovery_pitch": "ACS725LLCTR-20AB-T (Allegro MicroSystems LLC) component page with datasheet-verified CAD.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
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"files": [
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],
"visibility": {
"public": true
},
"updated_at": "2026-09-24T15:32:07.132Z"
}