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ACS725KMATR-30AB-T

ALLEGRO(美国埃戈罗) · IC · SOIC-16

ACS725KMATR-30AB-T from ALLEGRO(美国埃戈罗), in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IP+ passive Terminal for the current being sensed, fused internally, forming the primary conductor input.
2 IP+ passive Terminal for the current being sensed, fused internally, forming the primary conductor input.
3 IP+ passive Terminal for the current being sensed, fused internally, forming the primary conductor input.
4 IP+ passive Terminal for the current being sensed, fused internally, forming the primary conductor input.
5 IP- passive Terminal for the current being sensed, fused internally, forming the primary conductor return.
6 IP- passive Terminal for the current being sensed, fused internally, forming the primary conductor return.
7 IP- passive Terminal for the current being sensed, fused internally, forming the primary conductor return.
8 IP- passive Terminal for the current being sensed, fused internally, forming the primary conductor return.
9 NC unconnected No internal connection; recommended to be left unconnected to maintain high creepage.
10 VCC power_in Device power supply terminal; the part operates from 3 to 3.6 V single supply per the datasheet.
11 NC unconnected No internal connection; recommended to connect to GND for the best ESD performance.
12 VIOUT output Analog output signal that changes proportionally with the bidirectional AC or DC primary sensed current.
13 FILTER passive Terminal for an external capacitor that sets the bandwidth of the output filter.
14 NC unconnected No internal connection; recommended to connect to GND for the best ESD performance.
15 GND power_in Signal ground terminal.
16 NC unconnected No internal connection; recommended to be left unconnected to maintain high creepage.

Key specifications

Parameter Value
Manufacturer ALLEGRO(美国埃戈罗)
Package SOIC-16
Category
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 3 3.3 3.6 V 5
Supply Current ICC 10 14 mA VCC within VCC(min) and VCC(max) 5
Output Capacitance Load CL 10 nF VIOUT to GND 5
Output Resistive Load RL 4.7 kΩ VIOUT to GND 5
Saturation Voltage Low VOL 0.3 V RL = 4.7 kΩ, TA = 25°C 5
Total Output Error ETOT -2.5 1 2.5 % IP = IPR(max), TA = 25°C to 125°C 7
Total Output Error ETOT -2.5 2.5 2.5 % IP = IPR(max), TA = -40°C to 25°C 7
Sensitivity Error ESENS -2 1 2 % TA = 25°C to 125°C, measured at IP = IPR(max) 7
Sensitivity Error ESENS -2.4 2.4 2.4 % TA = -40°C to 25°C, measured at IP = IPR(max) 7
Offset Voltage VOE -15 5 15 mV IP = 0 A, TA = 25°C to 125°C 7
Offset Voltage VOE -11 11 11 mV IP = 0 A, TA = -40°C to 25°C 7
Sensitivity Error Lifetime Drift Esens_drift -1 1 1 % 7
Total Output Error Lifetime Drift Etot_drift -1 1 1 % 7
Current Sensing Range IPR -30 30 A 7
Sensitivity Sens 44 mV/A IPR(min) < IP < IPR(max) 7
Nonlinearity ELIN -1 1 1 % Through full range of IP 5
Hall Plate Sensitivity Matching SensMATCH -1 1 1 % TA = 25°C 5
Primary Conductor Resistance RIP 0.85 mΩ TA = 25°C 5
Internal Filter Resistance RF(INT) 1.7 kΩ 5
Common Mode Field Rejection Ratio CMFRR 40 dB Uniform external magnetic field 5
Primary Hall Coupling Factor G1 4.5 G/A TA = 25°C 5
Secondary Hall Coupling Factor G2 0.5 G/A TA = 25°C 5
Hysteresis IHYS 150 mA Difference in offset after a ±40 A pulse 5
Rise Time tr 3 μs IP = IP(max), TA = 25°C, CL = 1 nF 5
Propagation Delay tpd 2 μs IP = IP(max), TA = 25°C, CL = 1 nF 5
Response Time tRESPONSE 4 μs IP = IP(max), TA = 25°C, CL = 1 nF 5
Internal Bandwidth BW 120 kHz Small signal -3 dB, CL = 1 nF 5
Noise Density IND 618 µARMS/√Hz Input-referenced noise density; TA = 25°C, CL = 1 nF 5
Noise IN 91 mARMS Input-referenced noise; CF = 4.7 nF, CL = 1 nF, BW = 18 kHz, TA= 25°C 5
Sensitivity Ratiometry Coefficient SENS_RAT_COEF 1.3 VCC = 3.0 to 3.6 V, TA = 25°C 5
Zero-Current Output Ratiometry Coefficient QVO_RAT_COEF 1 VCC = 3.0 to 3.6 V, TA = 25°C 5
Power-On Time tPO 80 μs Output reaches 90% of steady-state level, TA = 25°C, IP = IPR(max) applied 5
Shorted Output to Ground Current ISC(GND) 3.3 mA TA = 25°C 5
Shorted Output to VCC Current ISC(VCC) 45 mA TA = 25°C 5
Supply Voltage VCC 6 V 3
Reverse Supply Voltage VRCC -0.1 V 3
Reverse Output Voltage VRIOUT -0.1 V 3
Operating Ambient Temperature TA -40 125 °C Range K 3
Junction Temperature TJ(max) 165 °C 3
Storage Temperature Tstg -65 165 °C 3
Human Body Model ESD VHBM -2 2 kV Per AEC-Q100 3
Charged Device Model ESD VCDM -1 1 kV Per AEC-Q100 3
Junction-to-Ambient Thermal Resistance RθJA 23 °C/W Mounted on the Allegro ASEK724/5 MA evaluation board 3
Junction-to-Lead Thermal Resistance RθJL 5 °C/W Mounted on the Allegro ASEK724/5 MA evaluation board 3
Dielectric Surge Strength Test Voltage VSURGE 10000 V Tested ±5 pulses at 2/minute per IEC 61000-4-5, 1.2 µs (rise) / 50 µs (width) 3
Dielectric Strength Test Voltage VISO 4800 VRMS Agency type-tested for 60 seconds per UL 60950-1 (edition 2) 3
Working Voltage for Basic Isolation VWVBI 1097 VRMS Maximum approved working voltage for basic (single) isolation per UL 60950-1 (edition 2) 3
Working Voltage for Reinforced Isolation VWVRI 565 VRMS Maximum approved working voltage for reinforced isolation per UL 60950-1 (edition 2) 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper primary copper conduction path (from pins 1 through 4, to 1

CAD (KiCad official)

  • Symbol: ACS725KMATR-30AB-T
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: acs725kmatr-30ab-t-etched.step / acs725kmatr-30ab-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); acs725kmatr-30ab-t.step / acs725kmatr-30ab-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ALLEGRO(美国埃戈罗) datasheet (19 pp, sha256 95e92f8112aeddcd, retrieved 2026-11-02, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF