# ACS724LLCTR-50AB-T

**Allegro MicroSystems LLC** · Current Sensors · SOIC-8

ACS724LLCTR-50AB-T from Allegro MicroSystems LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for the current being sensed, fused internally, and part of the primary conductor path (pins 1 and 2 to pins 3 and 4) that has 1.2 mΩ typical resistance. |
| 2 | IP+ | passive | Terminal for the current being sensed, fused internally, and part of the primary conductor path (pins 1 and 2 to pins 3 and 4) that has 1.2 mΩ typical resistance. |
| 3 | IP- | passive | Terminal for the current being sensed, fused internally, and the return end of the primary conductor path; the output has a positive slope when current flows from pins 1 and 2 to pins 3 and 4. |
| 4 | IP- | passive | Terminal for the current being sensed, fused internally, and the return end of the primary conductor path; the output has a positive slope when current flows from pins 1 and 2 to pins 3 and 4. |
| 5 | GND | power_in | Signal ground terminal, electrically isolated from the primary conductor terminals (pins 1 through 4). |
| 6 | FILTER | passive | Terminal for an external capacitor that sets the output bandwidth, working with the internal filter resistance RF(int) of 1.8 kΩ typical (typical application uses CF = 1 nF). |
| 7 | VIOUT | output | Analog output signal that changes proportionally with the bidirectional primary sensed current; the datasheet requires a load of at least 4.7 kΩ and at most 10 nF to GND. |
| 8 | VCC | power_in | Device power supply terminal, specified for 4.5 to 5.5 V operation (absolute maximum 6 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | SOIC-8 |
| Category | Magnetic Sensors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 |  | 5.5 | V |  | 5 |
| Supply Current | ICC |  | 10 | 14 | mA | VCC = 5 V, output open | 5 |
| Output Capacitance Load | CL |  |  | 10 | nF | VIOUT to GND | 5 |
| Output Resistive Load | RL | 4.7 |  |  | kΩ | VIOUT to GND | 5 |
| Nonlinearity | ELIN | -1.5 |  | 1.5 | % | Through full range of IP | 5 |
| Current Sensing Range | IPR | -50 |  | 50 | A |  | 15 |
| Total Output Error (25°C to 150°C) | ETOT | -2 | 0.8 | 2 | % | IP = IPR(max), TA = 25°C to 150°C | 15 |
| Total Output Error (-40°C to 25°C) | ETOT | -6 | 4 | 6 | % | IP = IPR(max), TA = -40°C to 25°C | 15 |
| Sensitivity Error (25°C to 150°C) | Esens | -1.5 | 0.8 | 1.5 | % | IP = IPR(max), TA = 25°C to 150°C | 15 |
| Sensitivity Error (-40°C to 25°C) | Esens | -5.5 | 4 | 5.5 | % | IP = IPR(max), TA = -40°C to 25°C | 15 |
| Voltage Offset Error (25°C to 150°C) | VOE | -10 | 6 | 10 | mV | IP = 0 A, TA = 25°C to 150°C | 15 |
| Voltage Offset Error (-40°C to 25°C) | VOE | -30 | 6 | 30 | mV | IP = 0 A, TA = -40°C to 25°C | 15 |
| Sensitivity Error Lifetime Drift | Esens_drift | -3 | 1 | 3 | % |  | 15 |
| Total Output Error Lifetime Drift | Etot_drift | -3 | 1 | 3 | % |  | 15 |
| Supply Voltage (absolute maximum) | VCC |  |  | 6 | V |  | 3 |
| Reverse Supply Voltage | VRCC | -0.1 |  |  | V |  | 3 |
| Reverse Output Voltage | VRIOUT | -0.1 |  |  | V |  | 3 |
| Maximum Continuous Current | ICMAX |  |  | 55 | A | TA = 25°C | 3 |
| Operating Ambient Temperature (Range L) | TA | -40 |  | 150 | °C | Range L | 3 |
| Junction Temperature | TJ(max) |  |  | 165 | °C |  | 3 |
| Storage Temperature | Tstg | -65 |  | 165 | °C |  | 3 |
| Package Thermal Resistance (Junction to Ambient) | RθJA |  | 23 |  | °C/W | Mounted on Allegro 85-0740 evaluation board with 1500 mm2 of 4 oz. copper on each side | 3 |
| Package Thermal Resistance (Junction to Lead) | RθJL |  | 5 |  | °C/W | Mounted on Allegro ASEK724 evaluation board | 3 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | through the primary copper conduction path (from pins 1 and | 1 |

## CAD (KiCad official)

- Symbol: `ACS724LLCTR-50AB-T`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `acs724llctr-50ab-t-etched.step` / `acs724llctr-50ab-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acs724llctr-50ab-t.step` / `acs724llctr-50ab-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems LLC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588909230590345216) (24 pp, sha256 `b9bcdc03fa944d78`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/acs724llctr-50ab-t-datasheet.pdf)