component
ACS724LLCTR-50AB-T-JSM
Public Made by Adomby adom
JSMSEMI Current Sensors, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownACS724LLCTR-50AB-T-JSM
JSMSEMI · Current Sensors · SOP-8
ACS724LLCTR-50AB-T-JSM from JSMSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Primary current input, positive side. Current flows into the chip in the positive direction. Pins 1 and 2 are internally tied and form one terminal of the ~0.85 mΩ integrated primary conductor; both must be soldered together to carry the full sensed current (up to ±50 A continuous at 25 °C). |
| 2 | IP+ | passive | Primary current input, positive side (tied to pin 1). Second lead of the primary conductor's positive terminal; parallel with pin 1 to reduce trace resistance and carry rated primary current. |
| 3 | IP- | passive | Primary current return, negative side. Current flows out of the chip in the negative direction. Pins 3 and 4 are internally tied and form the negative terminal of the integrated primary conductor; both must be soldered to carry rated current and provide the required isolation creepage (4 mm) from the low-voltage side. |
| 4 | IP- | passive | Primary current return, negative side (tied to pin 3). Second lead of the primary conductor's negative terminal; parallel with pin 3 for full rated primary current. |
| 5 | GND | power_in | Device signal ground for the low-voltage side. Return for VCC, VIOUT, and FILTER; bypass VCC to this pin with 100 nF. |
| 6 | FILTER | passive | Bandwidth-setting pin. Connect an external capacitor CF (typically 1 nF) from this pin to GND to set the internal low-pass filter bandwidth and roll off output noise; default gives ~250 kHz internal bandwidth with the recommended 1 nF. |
| 7 | VIOUT | output | Analog output voltage proportional to the sensed primary current. Ratiometric bipolar output centered at VCC/2 (0 A quiescent) with ±40 mV/A typical sensitivity for the -50AB variant at VCC = 5 V. Drive up to 4.7 kΩ / 10 nF load; output swing 0.1 V to VCC−0.1 V. |
| 8 | VCC | power_in | Device power supply for the low-voltage side. 4.5 V-5.5 V for ACS724 (5 V nominal, ICC ≈ 10 mA typ). Bypass to GND (pin 5) with a 100 nF ceramic capacitor placed close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-8 |
| Category | Sensor |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
ACS724LLCTR-50AB-T-JSM
CAD (KiCad official)
- Symbol:
ACS724LLCTR-50AB-T-JSM - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
acs724llctr-50ab-t-jsm-etched.step/acs724llctr-50ab-t-jsm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs724llctr-50ab-t-jsm.step/acs724llctr-50ab-t-jsm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JSMSEMI datasheet (16 pp, sha256
b0dfb2b3df2c3bec, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).