# ACS724LLCTR-2P5AB-S

**Allegro MicroSystems, LLC** · Current Sensors · SOIC-8

ACS724LLCTR-2P5AB-S from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for the current being sensed, fused internally, forming part of the primary conductor path with 1.2 mΩ typical primary conductor resistance. |
| 2 | IP+ | passive | Terminal for the current being sensed, fused internally, forming part of the primary conductor path with 1.2 mΩ typical primary conductor resistance. |
| 3 | IP- | passive | Terminal for the current being sensed, fused internally, forming the return end of the primary conductor path with 1.2 mΩ typical primary conductor resistance. |
| 4 | IP- | passive | Terminal for the current being sensed, fused internally, forming the return end of the primary conductor path with 1.2 mΩ typical primary conductor resistance. |
| 5 | GND | power_in | Signal ground terminal for the sensor leads. |
| 6 | FILTER | passive | Terminal for an external capacitor that sets the output bandwidth, forming an RC circuit with the internal filter resistance RF(int) of 1.8 kΩ typical. |
| 7 | VIOUT | output | Analog output signal that is proportional to the primary sensed current, with a maximum output capacitive load of 10 nF and a minimum resistive load of 4.7 kΩ to GND. |
| 8 | VCC | power_in | Device power supply terminal, operating from 4.5 to 5.5 V with an absolute maximum supply voltage of 6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8 |
| Category | Magnetic Sensors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Current Sensing Range | IPR | -2.5 |  | 2.5 | A |  | 6 |
| Total Output Error | ETOT | -2.5 | 1.5 | 2.5 | % | IP = IPR(max), TA = 25°C to 150°C | 6 |
| Total Output Error | ETOT | -6.5 | 4.5 | 6.5 | % | IP = IPR(max), TA = -40°C to 25°C | 6 |
| Sensitivity Error | Esens | -2 | 1 | 2 | % | IP = IPR(max), TA = 25°C to 150°C | 6 |
| Sensitivity Error | Esens | -6 | 4.5 | 6 | % | IP = IPR(max), TA = -40°C to 25°C | 6 |
| Voltage Offset Error | VOE | -20 | 7 | 20 | mV | IP = 0 A, TA = 25°C to 150°C | 6 |
| Voltage Offset Error | VOE | -40 | 13 | 40 | mV | IP = 0 A, TA = -40°C to 25°C | 6 |
| Sensitivity Error Lifetime Drift | Esens_drift | -3 | 1 | 3 | % |  | 6 |
| Total Output Error Lifetime Drift | Etot_drift | -3 | 1 | 3 | % |  | 6 |
| Supply Voltage | VCC | 4.5 |  | 5.5 | V |  | 5 |
| Supply Current | ICC |  | 10 | 14 | mA | VCC = 5 V, output open | 5 |
| Output Capacitance Load | CL |  |  | 10 | nF | VIOUT to GND | 5 |
| Output Resistive Load | RL | 4.7 |  |  | kΩ | VIOUT to GND | 5 |
| Nonlinearity | ELIN | -1.5 |  | 1.5 | % | Through full range of IP | 5 |
| Supply Voltage | VCC |  |  | 6 | V |  | 3 |
| Reverse Supply Voltage | VRCC | -0.1 |  |  | V |  | 3 |
| Reverse Output Voltage | VRIOUT | -0.1 |  |  | V |  | 3 |
| Operating Ambient Temperature | TA | -40 |  | 150 | °C | Range L | 3 |
| Junction Temperature | TJ(max) |  |  | 165 | °C |  | 3 |
| Storage Temperature | Tstg | -65 |  | 165 | °C |  | 3 |
| Package Thermal Resistance (Junction to Ambient) | RθJA |  | 23 |  | °C/W | Mounted on the Allegro 85-0740 evaluation board with 1500 mm2 of 4 oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with thermal vias | 3 |
| Package Thermal Resistance (Junction to Lead) | RθJL |  | 5 |  | °C/W | Mounted on the Allegro ASEK724 evaluation board | 3 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | primary copper conduction path (from pins 1 and 2, to pins 3 | 1 |

## CAD (KiCad official)

- Symbol: `ACS724LLCTR-2P5AB-S`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `acs724llctr-2p5ab-s-etched.step` / `acs724llctr-2p5ab-s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acs724llctr-2p5ab-s.step` / `acs724llctr-2p5ab-s.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/acs724llctr-2p5ab-s-datasheet.pdf) (25 pp, sha256 `3e5631e2cc66f80d`, retrieved 2026-11-05, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/acs724llctr-2p5ab-s-datasheet.pdf)