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ACS724LLCTR-05AU-T

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Allegro MicroSystems, LLC Current Sensors, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsensorsacs724llctr-05au-tfactory-2.0.0extractor-text

Verified ACS724LLCTR-05AU-T

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ACS724LLCTR-05AU-T · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C2155520, digikey 620-ACS724LLCTR-05AU-TTR-ND, mouser 250-724LLCTR05AUT
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-mxul46ab/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ acs724llctr-05au-t.kicad_sym✓ acs724llctr-05au-t.kicad_mod✓ acs724llctr-05au-t.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers acs724llctr-05au-t: viewers · Ray 3d ago
acs724llctr-05au-t-etched.glb Publish 0.1.0 · Ray 3d ago
acs724llctr-05au-t-etched.step acs724llctr-05au-t: factory component page (tier=lcsc) · Ray 3d ago
acs724llctr-05au-t-hero.glb acs724llctr-05au-t: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
acs724llctr-05au-t-hero.overlay.json Publish 0.1.0 · Ray 3d ago
acs724llctr-05au-t.glb Publish 0.1.0 · Ray 3d ago
acs724llctr-05au-t.kicad_mod Publish 0.1.0 · Ray 3d ago
acs724llctr-05au-t.kicad_sym Publish 0.1.0 · Ray 3d ago
acs724llctr-05au-t.lbr Publish 0.1.0 · Ray 3d ago
acs724llctr-05au-t.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
verification.json Verified: Published by the parts factory: tier lcsc, 8 pins · Ray 3d ago

ACS724LLCTR-05AU-T

Allegro MicroSystems, LLC · Current Sensors · SOIC-8

ACS724LLCTR-05AU-T from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IP+ passive Terminal for the primary current being sensed, fused internally, forming the input end of the 1.2 mΩ typical primary conductor path to pins 3 and 4.
2 IP+ passive Terminal for the primary current being sensed, fused internally, forming the input end of the 1.2 mΩ typical primary conductor path to pins 3 and 4.
3 IP- passive Terminal for the primary current being sensed, fused internally, forming the output end of the primary conductor path from pins 1 and 2.
4 IP- passive Terminal for the primary current being sensed, fused internally, forming the output end of the primary conductor path from pins 1 and 2.
5 GND power_in Signal ground terminal for the sensor IC.
6 FILTER passive Terminal for an external capacitor CF that sets the output bandwidth together with the internal filter resistance RF(int) of 1.8 kΩ typical.
7 VIOUT output Analog output signal that changes proportionally with the bidirectional sensed primary current, with VOH limited to VCC - 0.3 V and VOL to 0.3 V at RL = 4.7 kΩ.
8 VCC power_in Device power supply terminal, specified for 4.5 to 5.5 V.

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package SOIC-8
Category Sensors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 4.5 5.5 V 5
Supply Current ICC 10 14 mA VCC = 5 V, output open 5
Output Capacitance Load CL 10 nF VIOUT to GND 5
Output Resistive Load RL 4.7 kΩ VIOUT to GND 5
Primary Conductor Resistance RIP 1.2 mΩ TA = 25°C 5
Primary Conductor Inductance LIP 2 nH TA = 25°C 5
Internal Filter Resistance RF(int) 1.8 kΩ 5
Common Mode Field Rejection Ratio CMFRR 40 dB Uniform external magnetic field 5
Primary Hall Coupling Factor G1 11 G/A TA = 25°C 5
Secondary Hall Coupling Factor G2 2.8 G/A TA = 25°C 5
Hall Plate Sensitivity Matching Sensmatch -1 1 % TA = 25°C 5
Nonlinearity ELIN -1.5 1.5 % Through full range of IP 5
Rise Time tr 3 μs TA = 25°C, CL = 1 nF 5
Propagation Delay tpd 2 μs TA = 25°C, CL = 1 nF 5
Response Time tRESPONSE 4 μs TA = 25°C, CL = 1 nF 5
Output Slew Rate SR 0.53 V/μs TA = 25°C, CL = 1 nF 5
Bandwidth BW 120 kHz Small signal -3 dB; CL = 1 nF 5
Noise Density IND 150 µA(rms)/√Hz Input-referenced noise density; TA = 25°C, CL = 1 nF 5
Noise IN 20 mA(rms) Input-referenced noise: CF = 4.7 nF, CL = 1 nF, BW = 18 kHz, TA = 25°C 5
Sensitivity Ratiometry Coefficient SENS_RAT_COEF 1.3 VCC = 4.5 to 5.5 V, TA = 25°C 5
Zero-Current Output Ratiometry Coefficient QVO_RAT_COEF 1 VCC = 4.5 to 5.5 V, TA = 25°C 5
Saturation Voltage Low VOL 0.3 V RL = 4.7 kΩ 5
Power-On Time tPO 80 μs TA = 25°C 5
Shorted Output-to-Ground Current ISC(GND) 3.3 mA TA = 25°C 5
Shorted Output-to-VCC Current ISC(VCC) 45 mA TA = 25°C 5
Supply Voltage (absolute maximum) VCC 6 V 3
Reverse Supply Voltage VRCC -0.1 V 3
Reverse Output Voltage VRIOUT -0.1 V 3
Maximum Continuous Current ICMAX 55 A TA = 25°C 3
Operating Ambient Temperature Range L TA -40 150 °C 3
Junction Temperature TJ(max) 165 °C 3
Storage Temperature Tstg -65 165 °C 3
Human Body Model ESD Rating VHBM -3.5 3.5 kV Per AEC-Q100 3
Charged Device Model ESD Rating VCDM -1 1 kV Per AEC-Q100 3
Package Thermal Resistance (Junction to Ambient) RθJA 23 °C/W Mounted on Allegro 85-0740 evaluation board with 1500 mm2 of 4 oz. copper on each side 3
Package Thermal Resistance (Junction to Lead) RθJL 5 °C/W Mounted on Allegro ASEK724 evaluation board 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper through the primary copper conduction path (from pins 1 and 1

CAD (KiCad official)

  • Symbol: ACS724LLCTR-05AU-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: acs724llctr-05au-t-etched.step / acs724llctr-05au-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); acs724llctr-05au-t.step / acs724llctr-05au-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (25 pp, sha256 1b172b64e8e1a4c5, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF