component
ACS723LLCTR-05AB-T
Public Made by Adomby adom
Allegro MicroSystems LLC Current Sensors, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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ACS723LLCTR-05AB-T
Allegro MicroSystems LLC · Current Sensors · SOIC-8
ACS723LLCTR-05AB-T from Allegro MicroSystems LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Positive terminal of the internal primary current-sense conductor; tie to pin 2 externally. Fused internally, 0.65 mΩ path resistance, 65 A ICMAX at 25 °C. |
| 2 | IP+ | passive | Positive terminal of the internal primary current-sense conductor; tie to pin 1 externally. Fused internally, 0.65 mΩ path resistance. |
| 3 | IP- | passive | Negative terminal of the internal primary current-sense conductor; tie to pin 4 externally. Fused internally; galvanically isolated (2.4 kVrms dielectric strength) from the signal pins 5-8. |
| 4 | IP- | passive | Negative terminal of the internal primary current-sense conductor; tie to pin 3 externally. Fused internally; galvanically isolated from signal-side pins. |
| 5 | GND | power_in | Signal ground reference for VCC, VIOUT, and BW_SEL. Isolated from the primary conductor (IP+/IP-). |
| 6 | BW_SEL | input | Bandwidth-select input. Leave floating (or tie to VCC) for 20 kHz low-noise mode; tie to GND for 80 kHz high-bandwidth mode. |
| 7 | VIOUT | output | Analog output voltage, ratiometric to VCC. Bidirectional signal centered at VCC/2 with 400 mV/A sensitivity for the -05AB variant (±5 A full-scale range). Recommend a CL bypass capacitor from VIOUT to GND. |
| 8 | VCC | power_in | Device supply voltage input, 4.5 V to 5.5 V (nominal 5 V). Absolute maximum 6 V. Decouple to GND with a 0.1 µF ceramic capacitor (CBYPASS). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | SOIC-8 |
| Category | Magnetic Sensors |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
ACS723LLCTR-05AB-TACS723LLCTR-10AU-TACS723LLCTR-10AB-TACS723LLCTR-20AU-TACS723LLCTR-20AB-TACS723LLCTR-40AU-TACS723LLCTR-40AB-TACS723LLCTR-50AB-T
CAD (KiCad official)
- Symbol:
ACS723LLCTR-05AB-T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
acs723llctr-05ab-t-etched.step/acs723llctr-05ab-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs723llctr-05ab-t.step/acs723llctr-05ab-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (24 pp, sha256
29b651eb6a6c9277, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ACS723LLCTR-05AB-T
**Allegro MicroSystems LLC** · Current Sensors · SOIC-8
ACS723LLCTR-05AB-T from Allegro MicroSystems LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Positive terminal of the internal primary current-sense conductor; tie to pin 2 externally. Fused internally, 0.65 mΩ path resistance, 65 A ICMAX at 25 °C. |
| 2 | IP+ | passive | Positive terminal of the internal primary current-sense conductor; tie to pin 1 externally. Fused internally, 0.65 mΩ path resistance. |
| 3 | IP- | passive | Negative terminal of the internal primary current-sense conductor; tie to pin 4 externally. Fused internally; galvanically isolated (2.4 kVrms dielectric strength) from the signal pins 5-8. |
| 4 | IP- | passive | Negative terminal of the internal primary current-sense conductor; tie to pin 3 externally. Fused internally; galvanically isolated from signal-side pins. |
| 5 | GND | power_in | Signal ground reference for VCC, VIOUT, and BW_SEL. Isolated from the primary conductor (IP+/IP-). |
| 6 | BW_SEL | input | Bandwidth-select input. Leave floating (or tie to VCC) for 20 kHz low-noise mode; tie to GND for 80 kHz high-bandwidth mode. |
| 7 | VIOUT | output | Analog output voltage, ratiometric to VCC. Bidirectional signal centered at VCC/2 with 400 mV/A sensitivity for the -05AB variant (±5 A full-scale range). Recommend a CL bypass capacitor from VIOUT to GND. |
| 8 | VCC | power_in | Device supply voltage input, 4.5 V to 5.5 V (nominal 5 V). Absolute maximum 6 V. Decouple to GND with a 0.1 µF ceramic capacitor (CBYPASS). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | SOIC-8 |
| Category | Magnetic Sensors |
| Pins | 8 |
## Ordering variants
Same part, different packaging or reel option.
- `ACS723LLCTR-05AB-T`
- `ACS723LLCTR-10AU-T`
- `ACS723LLCTR-10AB-T`
- `ACS723LLCTR-20AU-T`
- `ACS723LLCTR-20AB-T`
- `ACS723LLCTR-40AU-T`
- `ACS723LLCTR-40AB-T`
- `ACS723LLCTR-50AB-T`
## CAD (KiCad official)
- Symbol: `ACS723LLCTR-05AB-T`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `acs723llctr-05ab-t-etched.step` / `acs723llctr-05ab-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acs723llctr-05ab-t.step` / `acs723llctr-05ab-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems LLC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588941876573442048) (24 pp, sha256 `29b651eb6a6c9277`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/acs723llctr-05ab-t-datasheet.pdf)