# ACS722LLCTR-40AB-T

**Allegro MicroSystems, LLC** · Current Sensors · SOIC-8

ACS722LLCTR-40AB-T from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for the primary current being sensed, fused internally; current flowing from pins 1 and 2 to pins 3 and 4 produces a positive output slope. |
| 2 | IP+ | passive | Terminal for the primary current being sensed, fused internally; current flowing from pins 1 and 2 to pins 3 and 4 produces a positive output slope. |
| 3 | IP- | passive | Terminal for the primary current being sensed, fused internally; the return end of the 0.65 mΩ primary conductor path. |
| 4 | IP- | passive | Terminal for the primary current being sensed, fused internally; the return end of the 0.65 mΩ primary conductor path. |
| 5 | GND | power_in | Signal ground terminal, electrically isolated from the primary conductor path (pins 1 to 4). |
| 6 | BW_SEL | input | Terminal for selecting the 20 kHz or 80 kHz bandwidth; grounding it selects the high bandwidth (80 kHz) mode. |
| 7 | VIOUT | output | Analog output signal that changes proportionally with the bidirectional or unidirectional primary sensed current. |
| 8 | VCC | power_in | Device power supply terminal, specified for 3 to 3.6 V single supply operation (VCC 3 to 3.6 V, typ 3.3 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8 |
| Category | Sensors |
| Pins | 8 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | primary copper conduction path (from pins 1 and 2, to pins 3 | 1 |

## CAD (KiCad official)

- Symbol: `ACS722LLCTR-40AB-T`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `acs722llctr-40ab-t-etched.step` / `acs722llctr-40ab-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acs722llctr-40ab-t.step` / `acs722llctr-40ab-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/acs722llctr-40ab-t-datasheet.pdf) (23 pp, sha256 `a3574a09b92a080b`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/acs722llctr-40ab-t-datasheet.pdf)