component
ACS722LLCTR-10AU-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Current Sensors, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 6d ago |
| viewers | 6d ago |
| acs722llctr-10au-t-etched.glb | 6d ago |
| acs722llctr-10au-t-etched.step | 6d ago |
| acs722llctr-10au-t-hero.glb | 6d ago |
| acs722llctr-10au-t-hero.overlay.json | 6d ago |
| acs722llctr-10au-t.glb | 6d ago |
| acs722llctr-10au-t.kicad_mod | 6d ago |
| acs722llctr-10au-t.kicad_sym | 6d ago |
| acs722llctr-10au-t.lbr | 6d ago |
| acs722llctr-10au-t.step | 6d ago |
| package.json | 6d ago |
| page.json | 6d ago |
| README.md | 6d ago |
ACS722LLCTR-10AU-T
Allegro MicroSystems, LLC · Current Sensors · SOP-8
ACS722LLCTR-10AU-T from Allegro MicroSystems, LLC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for current being sensed, fused internally with pin 2; current path (pins 1,2 to 3,4) has 0.65 mΩ typical resistance and is isolated from signal pins. |
| 2 | IP+ | passive | Terminal for current being sensed, fused internally with pin 1; current path (pins 1,2 to 3,4) has 0.65 mΩ typical resistance and is isolated from signal pins. |
| 3 | IP- | passive | Terminal for current being sensed, fused internally with pin 4; current path (pins 1,2 to 3,4) has 0.65 mΩ typical resistance and is isolated from signal pins. |
| 4 | IP- | passive | Terminal for current being sensed, fused internally with pin 3; current path (pins 1,2 to 3,4) has 0.65 mΩ typical resistance and is isolated from signal pins. |
| 5 | GND | power_in | Signal ground terminal. |
| 6 | BW_SEL | input | Bandwidth select terminal: tied to GND selects 80 kHz, tied to VCC selects 20 kHz. |
| 7 | VIOUT | output | Analog output signal proportional to sensed current; load of at least 4.7 kΩ and at most 10 nF to GND, absolute maximum 25 V. |
| 8 | VCC | power_in | Device power supply terminal, 3 V to 3.6 V operating (3.3 V typical), 6 V absolute maximum, with 0.1 µF bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOP-8 |
| Category | Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 3 | 3.3 | 3.6 | V | 6 | |
| Supply Current | ICC | 9 | 12 | mA | VCC within VCC(min) and VCC(max) | 6 | |
| Output Capacitance Load | CL | 10 | nF | VIOUT to GND | 6 | ||
| Output Resistive Load | RL | 4.7 | kΩ | VIOUT to GND | 6 | ||
| Primary Conductor Resistance | RIP | 0.65 | mΩ | TA = 25°C | 6 | ||
| Magnetic Coupling Factor | CF | 10 | G/A | 6 | |||
| Rise Time (BW_SEL to GND) | tr | 4 | μs | IP = IP(max), TA = 25°C, CL = 1 nF, BW_SEL tied to GND | 6 | ||
| Rise Time (BW_SEL to VCC) | tr | 17.5 | μs | IP = IP(max), TA = 25°C, CL = 1 nF, BW_SEL tied to VCC | 6 | ||
| Propagation Delay (BW_SEL to GND) | tpd | 1 | μs | IP = IP(max), TA = 25°C, CL = 1 nF, BW_SEL tied to GND | 6 | ||
| Propagation Delay (BW_SEL to VCC) | tpd | 5 | μs | IP = IP(max), TA = 25°C, CL = 1 nF, BW_SEL tied to VCC | 6 | ||
| Response Time (BW_SEL to GND) | tRESPONSE | 5 | μs | IP = IP(max), TA = 25°C, CL = 1 nF, BW_SEL tied to GND | 6 | ||
| Response Time (BW_SEL to VCC) | tRESPONSE | 22.5 | μs | IP = IP(max), TA = 25°C, CL = 1 nF, BW_SEL tied to VCC | 6 | ||
| Internal Bandwidth (BW_SEL to GND) | BWi | 80 | kHz | Small signal -3 dB; CL = 1 nF, BW_SEL tied to GND | 6 | ||
| Internal Bandwidth (BW_SEL to VCC) | BWi | 20 | kHz | Small signal -3 dB; CL = 1nF, BW_SEL tied to VCC | 6 | ||
| Noise Density | IND | 150 | µA(rms)/√Hz | Input referenced noise density; TA = 25°C, CL = 1 nF | 6 | ||
| Noise (80 kHz) | IN | 42 | mA(rms) | Input referenced noise; BWi = 80 kHz, TA = 25°C, CL = 1 nF | 6 | ||
| Noise (20 kHz) | IN | 21 | mA(rms) | Input referenced noise; BWi = 20 kHz, TA = 25°C, CL = 1 nF | 6 | ||
| Nonlinearity | ELIN | -1 | 1 | % | Through full range of IP | 6 | |
| Saturation Voltage Low | VOL | 0.33 | V | RL = 4.7 kΩ, TA = 25°C | 6 | ||
| Power-On Time | tPO | 64 | μs | Output reaches 90% of steady-state level, TA = 25°C, IP = IPR(max) applied | 6 | ||
| Current Sensing Range | IPR | 0 | 10 | A | 8 | ||
| Sensitivity | Sens | 264 | mV/A | IPR(min) < IP < IPR(max) | 8 | ||
| Sensitivity Error (25°C to 150°C) | Esens | -2 | 2 | % | TA = 25°C to 150°C; measured at IP = IPR(max) | 8 | |
| Sensitivity Error (-40°C to 25°C) | Esens | -2.5 | 2.5 | % | TA = -40°C to 25°C; measured at IP = IPR(max) | 8 | |
| Offset Voltage (25°C to 150°C) | VOE | -15 | 15 | mV | IP = 0 A; TA = 25°C to 150°C | 8 | |
| Offset Voltage (-40°C to 25°C) | VOE | -20 | 20 | mV | IP = 0 A; TA = -40°C to 25°C | 8 | |
| Total Output Error (25°C to 150°C) | ETOT | -2.5 | 2.5 | % | IP = IPR(max), TA = 25°C to 150°C | 8 | |
| Total Output Error (-40°C to 25°C) | ETOT | -3 | 3 | % | IP = IPR(max), TA = -40°C to 25°C | 8 | |
| Sensitivity Error Lifetime Drift | Esens_drift | -2 | 2 | % | 8 | ||
| Total Output Error Lifetime Drift | Etot_drift | -2 | 2 | % | 8 | ||
| Supply Voltage (abs max) | VCC | 6 | V | 3 | |||
| Reverse Supply Voltage | VRCC | -0.1 | V | 3 | |||
| Output Voltage | VIOUT | 25 | V | 3 | |||
| Reverse Output Voltage | VRIOUT | -0.1 | V | 3 | |||
| Maximum Continuous Current | ICMAX | 65 | A | TA = 25°C | 3 | ||
| Operating Ambient Temperature | TA | -40 | 150 | °C | Range L | 3 | |
| Junction Temperature | TJ(max) | 165 | °C | 3 | |||
| Storage Temperature | Tstg | -65 | 165 | °C | 3 | ||
| Thermal Resistance Junction to Ambient | RθJA | 23 | ºC/W | Mounted on the Allegro 85-0593 evaluation board with 400 mm2 of 4 oz. copper on each side | 3 | ||
| Thermal Resistance Junction to Lead | RθJL | 5 | ºC/W | Mounted on the Allegro ASEK 722 evaluation board | 3 | ||
| Dielectric Strength Test Voltage | VISO | 2400 | VRMS | Agency type-tested for 60 seconds per UL 60950-1 (edition. 2) | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | primary copper conduction path (from pins 1 and 2, to pins 3 | 1 |
CAD (KiCad official)
- Symbol:
ACS722LLCTR-10AU-T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
acs722llctr-10au-t-etched.step/acs722llctr-10au-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs722llctr-10au-t.step/acs722llctr-10au-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (23 pp, sha256
a3574a09b92a080b, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).