component
ACS720KLATR-35AB-T
Public Made by Adomby adom
Allegro MicroSystems LLC Current Sensors, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 9d ago |
| viewers | 9d ago |
| acs720klatr-35ab-t-etched.glb | 9d ago |
| acs720klatr-35ab-t-etched.step | 9d ago |
| acs720klatr-35ab-t-hero.glb | 9d ago |
| acs720klatr-35ab-t-hero.overlay.json | 9d ago |
| acs720klatr-35ab-t.glb | 9d ago |
| acs720klatr-35ab-t.kicad_mod | 9d ago |
| acs720klatr-35ab-t.kicad_sym | 9d ago |
| acs720klatr-35ab-t.lbr | 9d ago |
| acs720klatr-35ab-t.step | 9d ago |
| package.json | 9d ago |
| page.json | 9d ago |
| README.md | 9d ago |
ACS720KLATR-35AB-T
Allegro MicroSystems LLC · Current Sensors · SOIC-16-300mil
ACS720KLATR-35AB-T from Allegro MicroSystems LLC, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for the current being sensed, fused internally; pins 1 through 4 are tied together internally as IP+. |
| 2 | IP+ | passive | Terminal for the current being sensed, fused internally; pins 1 through 4 are tied together internally as IP+. |
| 3 | IP+ | passive | Terminal for the current being sensed, fused internally; pins 1 through 4 are tied together internally as IP+. |
| 4 | IP+ | passive | Terminal for the current being sensed, fused internally; pins 1 through 4 are tied together internally as IP+. |
| 5 | IP- | passive | Terminal for the current being sensed, fused internally; pins 5 through 8 are tied together internally as IP-. |
| 6 | IP- | passive | Terminal for the current being sensed, fused internally; pins 5 through 8 are tied together internally as IP-. |
| 7 | IP- | passive | Terminal for the current being sensed, fused internally; pins 5 through 8 are tied together internally as IP-. |
| 8 | IP- | passive | Terminal for the current being sensed, fused internally; pins 5 through 8 are tied together internally as IP-. |
| 9 | GND | power_in | Signal ground terminal for the device. |
| 10 | FAULT_S | output | Open-drain slow fault output, low true; intended to be pulled up to a compatible MCU voltage by the user. |
| 11 | FILTER | passive | Add a capacitor to set the output filter pole location (internal filter resistance RF(INT) is 1.7 kΩ typical). |
| 12 | VIOUT | output | Analog output signal, 0 to 3 V swing on a 5 V supply with 1.5 V at zero current; output capacitance load CL is limited to 10 nF maximum to GND. |
| 13 | FAULT_F | output | Open-drain fast fault output, low true; intended to be pulled up to a compatible MCU voltage by the user. |
| 14 | VCC | power_in | Device power supply terminal; operating range 4.5 V to 5.5 V (5.0 V typical), with 6 V absolute maximum. |
| 15 | VOC_F | input | Sets the trip current level for the fast fault via a user-created resistor divider from VCC. |
| 16 | VOC_S | input | Sets the trip current level for the slow fault via a user-created resistor divider from VCC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | SOIC-16-300mil |
| Category | Magnetic Sensors |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V | 5 | |
| Supply Current | ICC | 13 | 16 | mA | VCC = 5.0 V, output open | 5 | |
| Output Capacitance Load | CL | 10 | nF | VIOUT to GND | 5 | ||
| Output Resistive Load | RL | 10 | kΩ | VIOUT to GND, VIOUT to VCC | 5 | ||
| Saturation Voltage | VOL | 150 | mV | RL = 10 kΩ (VIOUT to VCC) | 5 | ||
| Clamp Voltage | VCLAMP | 3 | 3.25 | 3.5 | V | 5 | |
| Fault Output Low Voltage | VFAULTL | 0.4 | V | RPU = 10 kΩ, under fault condition, FAULT_S and FAULT_F pins | 6 | ||
| Fault Pull-Up Resistance | RPU | 4.7 | 500 | kΩ | 6 | ||
| Supply Voltage (absolute maximum) | VCC | 6 | V | 3 | |||
| Reverse Supply Voltage | VRCC | -0.5 | V | 3 | |||
| Filter Voltage | VFILTER | 25 | V | 3 | |||
| Reverse Filter Voltage | VRFILTER | -0.5 | V | 3 | |||
| Reverse Output Voltage | VRIOUT, VRFAULT_S, VRFAULT_F | -0.5 | V | 3 | |||
| Reverse Input Pin Voltages | VROC_S, VROC_F | -0.5 | V | 3 | |||
| Maximum Continuous Current | ICMAX | 55 | A | TA = 25°C | 3 | ||
| Operating Ambient Temperature | TA | -40 | 125 | °C | Range K | 3 | |
| Junction Temperature | TJ(max) | 165 | °C | 3 | |||
| Storage Temperature | Tstg | -65 | 170 | °C | 3 | ||
| Optimized Accuracy Range | IPR | -35 | 35 | A | x35AB variant | 9 | |
| Sensitivity Error | ESENS | -1.5 | 0.6 | 1.5 | % | IP = IPR(max), TA = 25°C to 125°C | 9 |
| Sensitivity Error | ESENS | -4 | 1.5 | 4 | % | IP = IPR(max), TA = -40°C to 25°C | 9 |
| Offset Voltage | VOE | -10 | 3.5 | 10 | mV | IP = 0 A, TA = 25°C to 125°C | 9 |
| Offset Voltage | VOE | -30 | 9 | 30 | mV | IP = 0 A, TA = -40°C to 25°C | 9 |
| Fast Fault Error (positive IP) | EFF(HIGH)+ | -10 | 5 | 10 | % | VOC_F = 0.7 × VCC, Positive IP, TA = 25°C | 9 |
| Fast Fault Error (negative IP) | EFF(HIGH)- | -10 | 5 | 10 | % | VOC_F = 0.7 × VCC, Negative IP, TA = 25°C | 9 |
| Fast Fault Error (negative IP) | EFF(HIGH)- | -15 | 10 | 15 | % | VOC_F = 0.7 × VCC, Negative IP, TA = 25°C to 125°C | 9 |
| Fast Fault Error (positive IP, low trip) | EFF(LOW)+ | -20 | 12 | 20 | % | VOC_F = 0.38 × VCC, Positive IP, TA = 25°C | 9 |
| Fast Fault Error (negative IP, low trip) | EFF(LOW)- | -20 | 12 | 20 | % | VOC_F = 0.38 × VCC, Negative IP, TA = 25°C | 9 |
| Fast Fault Error (negative IP, low trip) | EFF(LOW)- | -30 | 18 | 30 | % | VOC_F = 0.38 × VCC, Negative IP, TA = 25°C to 125°C | 9 |
| Slow Fault Error (high trip) | ESF(HIGH) | -6 | 3 | 6 | % | VOC_S = 0.7 × VCC, IP rising | 9 |
| Slow Fault Error (low trip) | ESF(LOW) | -10 | 5 | 10 | % | VOC_S = 0.3 × VCC, IP rising | 9 |
| Fast Fault Response Time | tR(FF) | 1.5 | 2 | μs | Current step 0 to 1.2 × IFAULT(FAST); RPU = 10 kΩ, 100 pF from FAULT_F to ground | 9 | |
| Junction-to-Ambient Thermal Resistance | RθJA | 17 | °C/W | Mounted on Allegro ASEK732/3 evaluation board | 4 | ||
| Junction-to-Lead Thermal Resistance | RθJL | 5 | °C/W | Mounted on Allegro ASEK732/3 evaluation board | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | [2] The Allegro evaluation board has 1500 mm2 of 2 oz. copper on each side, connected to pins 1 through 4 and pins 5 through 8, with thermal vias | 4 |
CAD (KiCad official)
- Symbol:
ACS720KLATR-35AB-T - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
acs720klatr-35ab-t-etched.step/acs720klatr-35ab-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs720klatr-35ab-t.step/acs720klatr-35ab-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (35 pp, sha256
21cf76f28d33786d, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).