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ACS720KLATR-15AB-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Current Sensors, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownACS720KLATR-15AB-T
Allegro MicroSystems, LLC · Current Sensors · SOIC-16-300mil
ACS720KLATR-15AB-T from Allegro MicroSystems, LLC, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for current being sensed, fused internally with pins 1 through 4 as the IP+ side of the primary conductor. |
| 2 | IP+ | passive | Terminal for current being sensed, fused internally with pins 1 through 4 as the IP+ side of the primary conductor. |
| 3 | IP+ | passive | Terminal for current being sensed, fused internally with pins 1 through 4 as the IP+ side of the primary conductor. |
| 4 | IP+ | passive | Terminal for current being sensed, fused internally with pins 1 through 4 as the IP+ side of the primary conductor. |
| 5 | IP- | passive | Terminal for current being sensed, fused internally with pins 5 through 8 as the IP- side of the primary conductor. |
| 6 | IP- | passive | Terminal for current being sensed, fused internally with pins 5 through 8 as the IP- side of the primary conductor. |
| 7 | IP- | passive | Terminal for current being sensed, fused internally with pins 5 through 8 as the IP- side of the primary conductor. |
| 8 | IP- | passive | Terminal for current being sensed, fused internally with pins 5 through 8 as the IP- side of the primary conductor. |
| 9 | GND | power_in | Signal ground terminal. |
| 10 | FAULT_S | output | Open drain slow fault output (low true), which can be pulled up to an MCU-compatible voltage; absolute maximum is VCC + 0.7 V. |
| 11 | FILTER | passive | Add a capacitor to set the output filter pole location; absolute maximum voltage is 25 V. |
| 12 | VIOUT | output | Analog output signal proportional to the sensed current, with a 1.5 V zero-current output and 0 to 3 V swing, and a 10 kΩ minimum resistive load. |
| 13 | FAULT_F | output | Open drain fast fault output (low true), which can be pulled up to an MCU-compatible voltage; absolute maximum is VCC + 0.7 V. |
| 14 | VCC | power_in | Device power supply terminal, operating at 4.5 to 5.5 V (5.0 V typical) with a 6 V absolute maximum. |
| 15 | VOC_F | input | Sets the trip current level for the fast fault, via a resistor divider from the supply; absolute maximum is VCC + 0.7 V. |
| 16 | VOC_S | input | Sets the trip current level for the slow fault, via a resistor divider from the supply; absolute maximum is VCC + 0.7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-16-300mil |
| Category | Sensors |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V | 5 | |
| Supply Current | ICC | 13 | 16 | mA | VCC = 5.0 V, output open | 5 | |
| Clamp Voltage | VCLAMP | 3 | 3.25 | 3.5 | V | 5 | |
| Output Capacitance Load | CL | 10 | nF | VIOUT to GND | 5 | ||
| Output Resistive Load | RL | 10 | kΩ | VIOUT to GND, VIOUT to VCC | 5 | ||
| Saturation Voltage | VOL | 150 | mV | RL = 10 kΩ (VIOUT to VCC) | 5 | ||
| Fault Output Low Voltage | VFAULTL | 0.4 | V | RPU = 10 kΩ, under fault condition, FAULT_S and FAULT_F pins | 6 | ||
| Fault Pull-Up Resistance | RPU | 4.7 | 500 | kΩ | 6 | ||
| Fast Fault Range | IFAULT(F) | 1 | 2.25 | A | Absolute value of IP; printed as 1.0 × IPR to 2.25 × IPR | 6 | |
| Slow Fault Range | IFAULT(S) | 0.5 | 1.25 | A | Absolute value of IP; printed as 0.5 × IPR to 1.25 × IPR | 6 | |
| VOC Input Range | VVOC | 0.3 | 0.7 | V | VOC_S, VOC_F; printed as 0.3 × VCC to 0.7 × VCC | 6 | |
| Optimized Accuracy Range | IPR | -15 | 15 | A | 7 | ||
| Total Output Error | ETOT | -1.5 | 0.8 | 1.5 | % | IP = IPR(max), TA = 25°C to 125°C | 7 |
| Total Output Error | ETOT | -4 | 1.6 | 4 | % | IP = IPR(max), TA = -40°C to 25°C | 7 |
| Sensitivity Error | ESENS | -1.5 | 0.6 | 1.5 | % | IP = IPR(max), TA = 25°C to 125°C | 7 |
| Sensitivity Error | ESENS | -4 | 1.6 | 4 | % | IP = IPR(max), TA = -40°C to 25°C | 7 |
| Offset Voltage | VOE | -10 | 4 | 10 | mV | IP = 0 A, TA = 25°C to 125°C | 7 |
| Offset Voltage | VOE | -30 | 9 | 30 | mV | IP = 0 A, TA = -40°C to 25°C | 7 |
| Fast Fault Error High Positive | EFF(HIGH)+ | -10 | 5 | 10 | % | VOC_F = 0.7 × VCC, Positive IP, TA = 25°C | 7 |
| Fast Fault Error High Positive | EFF(HIGH)+ | -15 | 5 | 15 | % | VOC_F = 0.7 × VCC, Positive IP, TA = 25°C to 125°C | 7 |
| Fast Fault Error High Negative | EFF(HIGH)- | -12 | 6 | 12 | % | VOC_F = 0.7 × VCC, Negative IP, TA = 25°C | 7 |
| Fast Fault Error High Negative | EFF(HIGH)- | -30 | 20 | 30 | % | VOC_F = 0.7 × VCC, Negative IP, TA = 25°C to 125°C | 7 |
| Fast Fault Error Low Positive | EFF(LOW)+ | -10 | 7 | 10 | % | VOC_F = 0.54 × VCC, Positive IP, TA = 25°C | 7 |
| Fast Fault Error Low Positive | EFF(LOW)+ | -15 | 10 | 15 | % | VOC_F = 0.54 × VCC, Positive IP, TA = 25°C to 125°C | 7 |
| Fast Fault Error Low Negative | EFF(LOW)- | -15 | 7 | 15 | % | VOC_F = 0.54 × VCC, Negative IP, TA = 25°C | 7 |
| Fast Fault Error Low Negative | EFF(LOW)- | -40 | 25 | 40 | % | VOC_F = 0.54 × VCC, Negative IP, TA = 25°C to 125°C | 7 |
| Slow Fault Error High | ESF(HIGH) | -6 | 3 | 6 | % | VOC_S = 0.7 × VCC, IP rising | 7 |
| Slow Fault Error Low | ESF(LOW) | -12 | 5 | 12 | % | VOC_S = 0.3 × VCC, IP rising | 7 |
| Fast Fault Response Time | tR(FF) | 1.5 | 2 | μs | Current step 0 to 1.2 × IFAULT(FAST); RPU = 10 kΩ, 100 pF from FAULT_F to ground | 7 | |
| Sensitivity | Sens | 90 | mV/A | 7 | |||
| Zero-Current Output Voltage | VIOUT(Q) | 1.5 | V | IP = 0 A | 7 | ||
| Fast Fault Trip Level High | IFF(HIGH) | 33.8 | A | VOC_F = 0.7 × VCC | 7 | ||
| Fast Fault Trip Level Low | IFF(LOW) | 26.3 | A | VOC_F = 0.54 × VCC | 7 | ||
| Slow Fault Trip Level High | ISF(HIGH) | 18.8 | A | VOC_S = 0.7 × VCC | 7 | ||
| Slow Fault Trip Level Low | ISF(LOW) | 7.5 | A | VOC_S = 0.3 × VCC | 7 | ||
| Slow Fault Response Time | tR(SF) | 13 | μs | Current step 0 to 1.2 × IFAULT(SLOW); RPU = 10 kΩ, 100 pF from FAULT_S to ground | 7 | ||
| Filter Resistance | RF(INT) | 1.7 | kΩ | TA = 25°C | 5 | ||
| Primary Conductor Resistance | RIP | 1 | mΩ | TA = 25°C | 5 | ||
| Internal Bandwidth | BW | 120 | kHz | Small signal -3 dB; CL = 1 nF | 5 | ||
| Nonlinearity | ELIN | 0.75 | % | 5 | |||
| Supply Voltage | VCC | 6 | V | 3 | |||
| Reverse Supply Voltage | VRCC | -0.5 | V | 3 | |||
| Filter Voltage | VFILTER | 25 | V | 3 | |||
| Output Voltages | VIOUT, VFAULT_S, VFAULT_F | 0.7 | V | VCC + 0.7 V | 3 | ||
| Maximum Continuous Current | ICMAX | 55 | A | TA = 25°C | 3 | ||
| Operating Ambient Temperature | TA | -40 | 125 | °C | Range K | 3 | |
| Junction Temperature | TJ(max) | 165 | °C | 3 | |||
| Storage Temperature | Tstg | -65 | 170 | °C | 3 | ||
| Junction-to-Ambient Thermal Resistance | RθJA | 17 | °C/W | Mounted on the Allegro ASEK732/3 evaluation board | 4 | ||
| Junction-to-Lead Thermal Resistance | RθJL | 5 | °C/W | Mounted on the Allegro ASEK732/3 evaluation board | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | [2] The Allegro evaluation board has 1500 mm2 of 2 oz. copper on each side, connected to pins 1 through 4 and pins 5 through 8, with thermal vias | 4 |
CAD (KiCad official)
- Symbol:
ACS720KLATR-15AB-T - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
acs720klatr-15ab-t-etched.step/acs720klatr-15ab-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs720klatr-15ab-t.step/acs720klatr-15ab-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (35 pp, sha256
21cf76f28d33786d, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).