# ACS715LLCTR-30A-T

**Allegro MicroSystems, LLC** · Current Sensors · SOIC-8

ACS715LLCTR-30A-T from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Input terminal for the current being sampled; fused internally. |
| 2 | IP+ | passive | Input terminal for the current being sampled; fused internally. |
| 3 | IP- | passive | Output terminal for the current being sampled; fused internally. |
| 4 | IP- | passive | Output terminal for the current being sampled; fused internally. |
| 5 | GND | power_in | Signal ground terminal. |
| 6 | FILTER | passive | Terminal for an external capacitor that sets the device bandwidth. |
| 7 | VIOUT | output | Analog output signal. |
| 8 | VCC | power_in | Device power supply terminal (5.0 V nominal, 4.5 V to 5.5 V supply range). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8 |
| Category | Sensors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V |  | 4 |
| Supply Current | ICC |  | 10 | 13 | mA | VCC = 5.0 V, output open | 4 |
| Output Capacitance Load | CLOAD |  |  | 10 | nF | VIOUT to GND | 4 |
| Output Resistive Load | RLOAD | 4.7 |  |  | kΩ | VIOUT to GND | 4 |
| Sensitivity | Sens | 125 |  | 137 | mV/A | Over full range of IP, TA = -40°C to 150°C | 6 |
| Electrical Output Voltage | VOE | -40 |  | 40 | mV | IP = 0 A, TA = 25°C | 6 |
| Electrical Output Voltage | VOE | -60 |  | 60 | mV | IP = 0 A, TA = -40°C to 150°C | 6 |
| Total Output Error | ETOT | -1.5 |  | 1.5 | % | IP = 30 A, IP applied for 5 ms; TA = 25°C | 6 |
| Total Output Error | ETOT | -5 |  | 5 | % | IP = 30 A, IP applied for 5 ms; TA = -40°C to 150°C | 6 |
| Optimized Accuracy Range | IP | 0 |  | 30 | A |  | 6 |
| Operating Internal Leadframe Temperature | TA | -40 |  | 150 | °C | L range | 4 |
| Supply Voltage | VCC |  |  | 8 | V |  | 2 |
| Reverse Supply Voltage | VRCC |  |  | -0.1 | V |  | 2 |
| Output Voltage | VIOUT |  |  | 8 | V |  | 2 |
| Reverse Output Voltage | VRIOUT |  |  | -0.1 | V |  | 2 |
| Output Current Source | IOUT(Source) |  |  | 3 | mA |  | 2 |
| Output Current Sink | IOUT(Sink) |  |  | 10 | mA |  | 2 |
| Overcurrent Transient Tolerance | IP |  |  | 100 | A | 1 pulse, 100 ms | 2 |
| Maximum Junction Temperature | TJ(max) |  |  | 165 | °C |  | 2 |
| Storage Temperature | Tstg | -65 |  | 170 | °C |  | 2 |
| Working Voltage for Basic Isolation | VWFSI |  |  | 354 | VDC or Vpk | Basic (single) isolation per UL 60950-1, 1st Edition | 2 |
| Working Voltage for Reinforced Isolation | VWFRI |  |  | 184 | VDC or Vpk | Reinforced (double) isolation per UL 60950-1, 1st Edition | 2 |
| Junction-to-Lead Thermal Resistance | RθJL |  | 5 |  | °C/W | Mounted on the Allegro ASEK 715 evaluation board | 4 |
| Junction-to-Ambient Thermal Resistance | RθJA |  | 23 |  | °C/W | Mounted on the Allegro 85-0322 evaluation board, includes the power consumed by the board | 4 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | [2] The Allegro evaluation board has 1500 mm2 of 2 oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with thermal vias connecting the layers. | 4 |

## CAD (KiCad official)

- Symbol: `ACS715LLCTR-30A-T`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `acs715llctr-30a-t-etched.step` / `acs715llctr-30a-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acs715llctr-30a-t.step` / `acs715llctr-30a-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/acs715llctr-30a-t-datasheet.pdf) (14 pp, sha256 `4142065f8ddffa84`, retrieved 2026-11-02, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/acs715llctr-30a-t-datasheet.pdf)