component
ACS715LLCTR-20A-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Current Sensors, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ACS715LLCTR-20A-T
Allegro MicroSystems, LLC · Current Sensors · SOIC-8
ACS715LLCTR-20A-T from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Input terminal for the current being sampled, fused internally with pin 2; primary conductor resistance is 1.2 mΩ typical. |
| 2 | IP+ | passive | Input terminal for the current being sampled, fused internally with pin 1; primary conductor resistance is 1.2 mΩ typical. |
| 3 | IP- | passive | Output terminal for the current being sampled, fused internally with pin 4; isolated from signal pins 5-8 (2.1 kVRMS minimum). |
| 4 | IP- | passive | Output terminal for the current being sampled, fused internally with pin 3; isolated from signal pins 5-8 (2.1 kVRMS minimum). |
| 5 | GND | power_in | Signal ground terminal. |
| 6 | FILTER | passive | Terminal for an external capacitor CF to ground that sets the device bandwidth; internal filter resistance is 1.7 kΩ. |
| 7 | VIOUT | output | Analog output signal, VCC × 0.1 at 0 A, with 4.7 kΩ minimum load and 10 nF maximum capacitive load to GND. |
| 8 | VCC | power_in | Device power supply terminal, 4.5 to 5.5 V (5.0 V typical), absolute maximum 8 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8 |
| Category | Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| Supply Current | ICC | 10 | 13 | mA | VCC = 5.0 V, output open | 4 | |
| Output Capacitance Load | CLOAD | 10 | nF | VIOUT to GND | 4 | ||
| Output Resistive Load | RLOAD | 4.7 | kΩ | VIOUT to GND | 4 | ||
| Sensitivity | Sens | 161 | 194 | mV/A | Over full range of IP, TA = -40°C to 150°C | 5 | |
| Electrical Output Voltage | VOE | -60 | 60 | mV | IP = 0 A | 5 | |
| Total Output Error | ETOT | -6 | 6 | % | IP = 20 A, IP applied for 5 ms; TA = -40°C to 150°C | 5 | |
| Optimized Accuracy Range | IP | 0 | 20 | A | 5 | ||
| Operating Internal Leadframe Temperature (L range) | TA | -40 | 150 | °C | L range | 4 | |
| Supply Voltage | VCC | 8 | V | 2 | |||
| Reverse Supply Voltage | VRCC | -0.1 | V | 2 | |||
| Output Voltage | VIOUT | 8 | V | 2 | |||
| Reverse Output Voltage | VRIOUT | -0.1 | V | 2 | |||
| Output Current Source | IOUT(Source) | 3 | mA | 2 | |||
| Output Current Sink | IOUT(Sink) | 10 | mA | 2 | |||
| Overcurrent Transient Tolerance | IP | 100 | A | 1 pulse, 100 ms | 2 | ||
| Nominal Operating Ambient Temperature, Range L | TA | -40 | 150 | °C | Range L | 2 | |
| Maximum Junction Temperature | TJ(max) | 165 | °C | 2 | |||
| Storage Temperature | Tstg | -65 | 170 | °C | 2 | ||
| Dielectric Strength Test Voltage | VISO | 2100 | VAC | Agency type-tested for 60 seconds per UL standard 60950-1, 1st Edition | 2 | ||
| Working Voltage for Basic Isolation | VWFSI | 354 | VDC or Vpk | Basic (single) isolation per UL 60950-1, 1st Edition | 2 | ||
| Working Voltage for Reinforced Isolation | VWFRI | 184 | VDC or Vpk | Reinforced (double) isolation per UL 60950-1, 1st Edition | 2 | ||
| Junction-to-Lead Thermal Resistance | RθJL | 5 | °C/W | Mounted on the Allegro ASEK 715 evaluation board | 4 | ||
| Junction-to-Ambient Thermal Resistance | RθJA | 23 | °C/W | Mounted on the Allegro 85-0322 evaluation board, includes the power consumed by the board | 4 | ||
| Primary Conductor Resistance | RPRIMARY | 1.2 | mΩ | TA = 25°C | 4 | ||
| Rise Time | tr | 3.5 | μs | IP = IP(max), TA = 25°C, COUT = 10 nF | 4 | ||
| Frequency Bandwidth | f | 80 | kHz | -3 dB, TA = 25°C; IP is 10 A peak-to-peak | 4 | ||
| Nonlinearity | ELIN | 1.5 | % | Over full range of IP, IP applied for 5 ms (printed ±1.5) | 4 | ||
| Power-On Time | tPO | 35 | µs | Output reaches 90% of steady-state level, no capacitor on FILTER pin; TJ=25; 20 A present on leadframe | 4 | ||
| Magnetic Coupling | 12 | G/A | 4 | ||||
| Internal Filter Resistance | RF(INT) | 1.7 | kΩ | 4 | |||
| Sensitivity | Sens | 185 | mV/A | Over full range of IP, IP applied for 5 ms; TA = 25°C | 5 | ||
| Noise | VNOISE(PP) | 21 | mV | Peak-to-peak, TA = 25°C, 2 kHz external filter, 185 mV/A programmed Sensitivity, CF = 47 nF, COUT = 10 nF, 2 kHz bandwidth | 5 | ||
| Zero Current Output Slope | ∆VOUT(Q) | 0.08 | mV/°C | TA = -40°C to 25°C | 5 | ||
| Zero Current Output Slope | ∆VOUT(Q) | 0.16 | mV/°C | TA = 25°C to 150°C | 5 | ||
| Sensitivity Slope | ∆Sens | 0.035 | mV/A/°C | TA = -40°C to 25°C | 5 | ||
| Sensitivity Slope | ∆Sens | 0.019 | mV/A/°C | TA = 25°C to 150°C | 5 | ||
| Total Output Error | ETOT | 1.5 | % | IP = 20 A, IP applied for 5 ms; TA = 25°C (printed ±1.5) | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | [2] The Allegro evaluation board has 1500 mm2 of 2 oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with thermal vias connecting the layers. | 4 |
CAD (KiCad official)
- Symbol:
ACS715LLCTR-20A-T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
acs715llctr-20a-t-etched.step/acs715llctr-20a-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs715llctr-20a-t.step/acs715llctr-20a-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (14 pp, sha256
4142065f8ddffa84, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ACS715LLCTR-20A-T
**Allegro MicroSystems, LLC** · Current Sensors · SOIC-8
ACS715LLCTR-20A-T from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Input terminal for the current being sampled, fused internally with pin 2; primary conductor resistance is 1.2 mΩ typical. |
| 2 | IP+ | passive | Input terminal for the current being sampled, fused internally with pin 1; primary conductor resistance is 1.2 mΩ typical. |
| 3 | IP- | passive | Output terminal for the current being sampled, fused internally with pin 4; isolated from signal pins 5-8 (2.1 kVRMS minimum). |
| 4 | IP- | passive | Output terminal for the current being sampled, fused internally with pin 3; isolated from signal pins 5-8 (2.1 kVRMS minimum). |
| 5 | GND | power_in | Signal ground terminal. |
| 6 | FILTER | passive | Terminal for an external capacitor CF to ground that sets the device bandwidth; internal filter resistance is 1.7 kΩ. |
| 7 | VIOUT | output | Analog output signal, VCC × 0.1 at 0 A, with 4.7 kΩ minimum load and 10 nF maximum capacitive load to GND. |
| 8 | VCC | power_in | Device power supply terminal, 4.5 to 5.5 V (5.0 V typical), absolute maximum 8 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8 |
| Category | Sensors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V | | 4 |
| Supply Current | ICC | | 10 | 13 | mA | VCC = 5.0 V, output open | 4 |
| Output Capacitance Load | CLOAD | | | 10 | nF | VIOUT to GND | 4 |
| Output Resistive Load | RLOAD | 4.7 | | | kΩ | VIOUT to GND | 4 |
| Sensitivity | Sens | 161 | | 194 | mV/A | Over full range of IP, TA = -40°C to 150°C | 5 |
| Electrical Output Voltage | VOE | -60 | | 60 | mV | IP = 0 A | 5 |
| Total Output Error | ETOT | -6 | | 6 | % | IP = 20 A, IP applied for 5 ms; TA = -40°C to 150°C | 5 |
| Optimized Accuracy Range | IP | 0 | | 20 | A | | 5 |
| Operating Internal Leadframe Temperature (L range) | TA | -40 | | 150 | °C | L range | 4 |
| Supply Voltage | VCC | | | 8 | V | | 2 |
| Reverse Supply Voltage | VRCC | -0.1 | | | V | | 2 |
| Output Voltage | VIOUT | | | 8 | V | | 2 |
| Reverse Output Voltage | VRIOUT | -0.1 | | | V | | 2 |
| Output Current Source | IOUT(Source) | | | 3 | mA | | 2 |
| Output Current Sink | IOUT(Sink) | | | 10 | mA | | 2 |
| Overcurrent Transient Tolerance | IP | | | 100 | A | 1 pulse, 100 ms | 2 |
| Nominal Operating Ambient Temperature, Range L | TA | -40 | | 150 | °C | Range L | 2 |
| Maximum Junction Temperature | TJ(max) | | | 165 | °C | | 2 |
| Storage Temperature | Tstg | -65 | | 170 | °C | | 2 |
| Dielectric Strength Test Voltage | VISO | | | 2100 | VAC | Agency type-tested for 60 seconds per UL standard 60950-1, 1st Edition | 2 |
| Working Voltage for Basic Isolation | VWFSI | | | 354 | VDC or Vpk | Basic (single) isolation per UL 60950-1, 1st Edition | 2 |
| Working Voltage for Reinforced Isolation | VWFRI | | | 184 | VDC or Vpk | Reinforced (double) isolation per UL 60950-1, 1st Edition | 2 |
| Junction-to-Lead Thermal Resistance | RθJL | | 5 | | °C/W | Mounted on the Allegro ASEK 715 evaluation board | 4 |
| Junction-to-Ambient Thermal Resistance | RθJA | | 23 | | °C/W | Mounted on the Allegro 85-0322 evaluation board, includes the power consumed by the board | 4 |
| Primary Conductor Resistance | RPRIMARY | | 1.2 | | mΩ | TA = 25°C | 4 |
| Rise Time | tr | | 3.5 | | μs | IP = IP(max), TA = 25°C, COUT = 10 nF | 4 |
| Frequency Bandwidth | f | | 80 | | kHz | -3 dB, TA = 25°C; IP is 10 A peak-to-peak | 4 |
| Nonlinearity | ELIN | | 1.5 | | % | Over full range of IP, IP applied for 5 ms (printed ±1.5) | 4 |
| Power-On Time | tPO | | 35 | | µs | Output reaches 90% of steady-state level, no capacitor on FILTER pin; TJ=25; 20 A present on leadframe | 4 |
| Magnetic Coupling | | | 12 | | G/A | | 4 |
| Internal Filter Resistance | RF(INT) | | 1.7 | | kΩ | | 4 |
| Sensitivity | Sens | | 185 | | mV/A | Over full range of IP, IP applied for 5 ms; TA = 25°C | 5 |
| Noise | VNOISE(PP) | | 21 | | mV | Peak-to-peak, TA = 25°C, 2 kHz external filter, 185 mV/A programmed Sensitivity, CF = 47 nF, COUT = 10 nF, 2 kHz bandwidth | 5 |
| Zero Current Output Slope | ∆VOUT(Q) | | 0.08 | | mV/°C | TA = -40°C to 25°C | 5 |
| Zero Current Output Slope | ∆VOUT(Q) | | 0.16 | | mV/°C | TA = 25°C to 150°C | 5 |
| Sensitivity Slope | ∆Sens | | 0.035 | | mV/A/°C | TA = -40°C to 25°C | 5 |
| Sensitivity Slope | ∆Sens | | 0.019 | | mV/A/°C | TA = 25°C to 150°C | 5 |
| Total Output Error | ETOT | | 1.5 | | % | IP = 20 A, IP applied for 5 ms; TA = 25°C (printed ±1.5) | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | [2] The Allegro evaluation board has 1500 mm2 of 2 oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with thermal vias connecting the layers. | 4 |
## CAD (KiCad official)
- Symbol: `ACS715LLCTR-20A-T`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `acs715llctr-20a-t-etched.step` / `acs715llctr-20a-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acs715llctr-20a-t.step` / `acs715llctr-20a-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/acs715llctr-20a-t-datasheet.pdf) (14 pp, sha256 `4142065f8ddffa84`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/acs715llctr-20a-t-datasheet.pdf)