component
ACS71240LLCBTR-050U5
Public Made by Adomby adom
Allegro MicroSystems, LLC Current Sensors, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ACS71240LLCBTR-050U5
Allegro MicroSystems, LLC · Current Sensors · SOIC-8
ACS71240LLCBTR-050U5 from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Positive terminal for the current being sensed; fused internally, and pins 1 and 2 are bonded together. |
| 2 | IP+ | passive | Positive terminal for the current being sensed; fused internally, and pins 1 and 2 are bonded together. |
| 3 | IP- | passive | Negative terminal for the current being sensed; fused internally, and pins 3 and 4 are bonded together. |
| 4 | IP- | passive | Negative terminal for the current being sensed; fused internally, and pins 3 and 4 are bonded together. |
| 5 | GND | power_in | Signal ground terminal; absolute maximum reverse supply voltage VCC(R) is -0.5 V. |
| 6 | FAULT | output | Overcurrent fault output, active low; absolute maximum FAULT voltage VFAULT is 25 V. |
| 7 | VIOUT | output | Analog output signal; absolute maximum output voltage VIOUT is VCC + 0.7 V. |
| 8 | VCC | power_in | Device power supply terminal; absolute maximum supply voltage VCC is 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8 |
| Category | Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (5 V variant) | VCC | 4.5 | 5 | 5.5 | V | 5 V variant | 6 |
| Supply Current | ICC | 10 | 12 | mA | 5 V variant, no load on VIOUT | 6 | |
| Output Capacitive Load | CL | 4.7 | nF | VIOUT to GND | 6 | ||
| Output Resistive Load | RL | 10 | kΩ | VIOUT to GND | 6 | ||
| Primary Conductor Resistance | RIP | 1.2 | mΩ | TA = 25°C, SOIC-8 package | 6 | ||
| Primary Conductor Inductance | LIP | 2 | nH | TA = 25°C, SOIC-8 package | 6 | ||
| Primary Hall Coupling Factor | G1 | 11 | G/A | TA = 25°C, SOIC-8 package | 6 | ||
| Secondary Hall Coupling Factor | G2 | -2.8 | G/A | TA = 25°C, SOIC-8 package | 6 | ||
| Common Mode Field Rejection | CMFR | 0.6 | mA/G | Offset due to DC common field, SOIC-8 package | 6 | ||
| Rise Time | tr | 3 | 4 | μs | TA = 25°C, CL = 1 nF | 6 | |
| Propagation Delay | tpd | 1.6 | 2.2 | μs | TA = 25°C, CL = 1 nF | 6 | |
| Response Time | tRESPONSE | 4 | 4.9 | μs | TA = 25°C, CL = 1 nF | 6 | |
| Output Slew Rate | SR | 0.53 | V/µs | TA = 25°C, CL = 1 nF | 6 | ||
| Bandwidth | BW | 120 | kHz | Small signal -3 dB; CL = 1 nF | 6 | ||
| Noise Density | IND | 100 | µARMS/√Hz | VCC = 5.0 V, input referred, TA = 25°C, CL = 1 nF | 6 | ||
| Noise | IN | 52 | mARMS | VCC = 5.0 V, input referred, TA = 25°C, CL = 1 nF | 6 | ||
| Nonlinearity | ELIN | -1 | 1 | % | Through full range of IP, SOIC-8 package | 6 | |
| PSRR DC to 1 kHz | PSRR | 40 | dB | VCC = VCC ±10%, TA = 25°C, DC to 1 kHz | 6 | ||
| PSRR 1 kHz to 20 kHz | PSRR | 30 | dB | VCC = VCC ±10%, TA = 25°C, 1 kHz to 20 kHz | 6 | ||
| PSRR 20 kHz to 60 kHz | PSRR | 20 | dB | VCC = VCC ±10%, TA = 25°C, 20 kHz to 60 kHz | 6 | ||
| Output Saturation Voltage Low | VSAT_L | 0.3 | V | RL = 10 kΩ | 6 | ||
| Power-On Time | tPO | 80 | μs | TA = 25°C | 6 | ||
| Shorted Output-to-Ground Current | ISC(GND) | 30 | mA | TA = 25°C | 6 | ||
| Shorted Output-to-VCC Current | ISC(VCC) | 1.8 | mA | TA = 25°C | 6 | ||
| FAULT Current Hysteresis | IF(HYS) | 3 | 12 | % | Percent of IPR(MAX) | 7 | |
| FAULT Output Pullup Resistor | RPU | 10 | 500 | kΩ | 7 | ||
| FAULT Output Voltage | VOL | 0.3 | V | RPU = 10 kΩ, during fault condition | 7 | ||
| FAULT Response Time | tFAULT | 1.5 | 2.5 | µs | Time from /IP/ rising above /IFAULT/ until VFAULT < VOL(MAX); 100 pF from FAULT to GND; input current step 20% above IFAULT with rise time ≤ 1 µs | 7 | |
| FAULT Error at 25°C | EF | -10 | 3.5 | 10 | % | IFAULT, TA = 25°C | 7 |
| FAULT Error at temperature extremes | EF | -10 | 5 | 10 | % | TA = -40°C or TA(MAX) | 7 |
| Optimized Sensing Range | IPR | 0 | 50 | A | 13 | ||
| Sensitivity | Sens | 80 | mV/A | IPR(min) < IP < IPR(max) | 13 | ||
| Zero-Current Output Voltage | VIOUT(Q) | 0.5 | V | Unidirectional, IP = 0 A | 13 | ||
| Total Output Error (25°C to 150°C) | ETOT | -2 | 1.1 | 2 | % | IP = IPR(max), TA = 25°C to 150°C | 13 |
| Total Output Error (-40°C to 25°C) | ETOT | -6 | 3.75 | 6 | % | IP = IPR(max), TA = -40°C to 25°C | 13 |
| Sensitivity Error (25°C to 150°C) | ESENS | -1.9 | 1.1 | 1.9 | % | IP = IPR(max), TA = 25°C to 150°C | 13 |
| Sensitivity Error (-40°C to 25°C) | ESENS | -5.5 | 3.8 | 5.5 | % | IP = IPR(max), TA = -40°C to 25°C | 13 |
| Voltage Offset Error (25°C to 150°C) | VOE | -10 | 4 | 10 | mV | IP = 0 A, TA = 25°C to 150°C | 13 |
| Voltage Offset Error (-40°C to 25°C) | VOE | -30 | 5.5 | 30 | mV | IP = 0 A, TA = -40°C to 25°C | 13 |
| Supply Voltage | VCC | 6 | V | 3 | |||
| Reverse Supply Voltage | VCC(R) | -0.5 | V | 3 | |||
| Reverse Output Voltage | VIOUT(R) | -0.5 | V | 3 | |||
| FAULT Voltage | VFAULT | 25 | V | 3 | |||
| Reverse FAULT Voltage | VFAULT(R) | -0.5 | V | 3 | |||
| Maximum Continuous Current | ICMAX | 55 | A | TA = 25°C, SOIC-8 package | 3 | ||
| Operating Ambient Temperature Range | TA | -40 | 150 | °C | Range L (SOIC-8 package) | 3 | |
| Junction Temperature | TJ(MAX) | 165 | °C | 3 | |||
| Storage Temperature Range | Tstg | -65 | 170 | °C | 3 | ||
| Dielectric Surge Strength Test Voltage | VSURGE | 6000 | V | Tested ±5 pulses at 2/minute per IEC 61000-4-5, 1.2 µs (rise) / 50 µs (width) | 3 | ||
| Dielectric Strength Test Voltage | VISO | 2400 | VRMS | Agency type-tested for 60 seconds per UL 60950-1 (edition 2) | 3 | ||
| Working Voltage for Basic Isolation | VWVBI | 420 | VPK or VDC | Maximum approved working voltage for basic isolation per UL 60950-1 (edition 2) | 3 | ||
| Human Body Model ESD | VHBM | -6.5 | 6.5 | kV | Per AEC-Q100, SOIC-8 package | 3 | |
| Charged Device Model ESD | VCDM | -1 | 1 | kV | Per AEC-Q100 | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 1500 mm2 of 4 oz. copper (0.1388 mm) connected to pins 1 and 2, | 20 |
CAD (KiCad official)
- Symbol:
ACS71240LLCBTR-050U5 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
acs71240llcbtr-050u5-etched.step/acs71240llcbtr-050u5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs71240llcbtr-050u5.step/acs71240llcbtr-050u5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (25 pp, sha256
bb47820aa99ea699, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ACS71240LLCBTR-050U5
**Allegro MicroSystems, LLC** · Current Sensors · SOIC-8
ACS71240LLCBTR-050U5 from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Positive terminal for the current being sensed; fused internally, and pins 1 and 2 are bonded together. |
| 2 | IP+ | passive | Positive terminal for the current being sensed; fused internally, and pins 1 and 2 are bonded together. |
| 3 | IP- | passive | Negative terminal for the current being sensed; fused internally, and pins 3 and 4 are bonded together. |
| 4 | IP- | passive | Negative terminal for the current being sensed; fused internally, and pins 3 and 4 are bonded together. |
| 5 | GND | power_in | Signal ground terminal; absolute maximum reverse supply voltage VCC(R) is -0.5 V. |
| 6 | FAULT | output | Overcurrent fault output, active low; absolute maximum FAULT voltage VFAULT is 25 V. |
| 7 | VIOUT | output | Analog output signal; absolute maximum output voltage VIOUT is VCC + 0.7 V. |
| 8 | VCC | power_in | Device power supply terminal; absolute maximum supply voltage VCC is 6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8 |
| Category | Sensors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (5 V variant) | VCC | 4.5 | 5 | 5.5 | V | 5 V variant | 6 |
| Supply Current | ICC | | 10 | 12 | mA | 5 V variant, no load on VIOUT | 6 |
| Output Capacitive Load | CL | | | 4.7 | nF | VIOUT to GND | 6 |
| Output Resistive Load | RL | 10 | | | kΩ | VIOUT to GND | 6 |
| Primary Conductor Resistance | RIP | | 1.2 | | mΩ | TA = 25°C, SOIC-8 package | 6 |
| Primary Conductor Inductance | LIP | | 2 | | nH | TA = 25°C, SOIC-8 package | 6 |
| Primary Hall Coupling Factor | G1 | | 11 | | G/A | TA = 25°C, SOIC-8 package | 6 |
| Secondary Hall Coupling Factor | G2 | | -2.8 | | G/A | TA = 25°C, SOIC-8 package | 6 |
| Common Mode Field Rejection | CMFR | | 0.6 | | mA/G | Offset due to DC common field, SOIC-8 package | 6 |
| Rise Time | tr | | 3 | 4 | μs | TA = 25°C, CL = 1 nF | 6 |
| Propagation Delay | tpd | | 1.6 | 2.2 | μs | TA = 25°C, CL = 1 nF | 6 |
| Response Time | tRESPONSE | | 4 | 4.9 | μs | TA = 25°C, CL = 1 nF | 6 |
| Output Slew Rate | SR | | 0.53 | | V/µs | TA = 25°C, CL = 1 nF | 6 |
| Bandwidth | BW | | 120 | | kHz | Small signal -3 dB; CL = 1 nF | 6 |
| Noise Density | IND | | 100 | | µARMS/√Hz | VCC = 5.0 V, input referred, TA = 25°C, CL = 1 nF | 6 |
| Noise | IN | | 52 | | mARMS | VCC = 5.0 V, input referred, TA = 25°C, CL = 1 nF | 6 |
| Nonlinearity | ELIN | -1 | | 1 | % | Through full range of IP, SOIC-8 package | 6 |
| PSRR DC to 1 kHz | PSRR | | 40 | | dB | VCC = VCC ±10%, TA = 25°C, DC to 1 kHz | 6 |
| PSRR 1 kHz to 20 kHz | PSRR | | 30 | | dB | VCC = VCC ±10%, TA = 25°C, 1 kHz to 20 kHz | 6 |
| PSRR 20 kHz to 60 kHz | PSRR | | 20 | | dB | VCC = VCC ±10%, TA = 25°C, 20 kHz to 60 kHz | 6 |
| Output Saturation Voltage Low | VSAT_L | | | 0.3 | V | RL = 10 kΩ | 6 |
| Power-On Time | tPO | | 80 | | μs | TA = 25°C | 6 |
| Shorted Output-to-Ground Current | ISC(GND) | | 30 | | mA | TA = 25°C | 6 |
| Shorted Output-to-VCC Current | ISC(VCC) | | 1.8 | | mA | TA = 25°C | 6 |
| FAULT Current Hysteresis | IF(HYS) | 3 | 12 | | % | Percent of IPR(MAX) | 7 |
| FAULT Output Pullup Resistor | RPU | 10 | | 500 | kΩ | | 7 |
| FAULT Output Voltage | VOL | | | 0.3 | V | RPU = 10 kΩ, during fault condition | 7 |
| FAULT Response Time | tFAULT | | 1.5 | 2.5 | µs | Time from /IP/ rising above /IFAULT/ until VFAULT < VOL(MAX); 100 pF from FAULT to GND; input current step 20% above IFAULT with rise time ≤ 1 µs | 7 |
| FAULT Error at 25°C | EF | -10 | 3.5 | 10 | % | IFAULT, TA = 25°C | 7 |
| FAULT Error at temperature extremes | EF | -10 | 5 | 10 | % | TA = -40°C or TA(MAX) | 7 |
| Optimized Sensing Range | IPR | 0 | | 50 | A | | 13 |
| Sensitivity | Sens | | 80 | | mV/A | IPR(min) < IP < IPR(max) | 13 |
| Zero-Current Output Voltage | VIOUT(Q) | | 0.5 | | V | Unidirectional, IP = 0 A | 13 |
| Total Output Error (25°C to 150°C) | ETOT | -2 | 1.1 | 2 | % | IP = IPR(max), TA = 25°C to 150°C | 13 |
| Total Output Error (-40°C to 25°C) | ETOT | -6 | 3.75 | 6 | % | IP = IPR(max), TA = -40°C to 25°C | 13 |
| Sensitivity Error (25°C to 150°C) | ESENS | -1.9 | 1.1 | 1.9 | % | IP = IPR(max), TA = 25°C to 150°C | 13 |
| Sensitivity Error (-40°C to 25°C) | ESENS | -5.5 | 3.8 | 5.5 | % | IP = IPR(max), TA = -40°C to 25°C | 13 |
| Voltage Offset Error (25°C to 150°C) | VOE | -10 | 4 | 10 | mV | IP = 0 A, TA = 25°C to 150°C | 13 |
| Voltage Offset Error (-40°C to 25°C) | VOE | -30 | 5.5 | 30 | mV | IP = 0 A, TA = -40°C to 25°C | 13 |
| Supply Voltage | VCC | | | 6 | V | | 3 |
| Reverse Supply Voltage | VCC(R) | -0.5 | | | V | | 3 |
| Reverse Output Voltage | VIOUT(R) | -0.5 | | | V | | 3 |
| FAULT Voltage | VFAULT | | | 25 | V | | 3 |
| Reverse FAULT Voltage | VFAULT(R) | -0.5 | | | V | | 3 |
| Maximum Continuous Current | ICMAX | | | 55 | A | TA = 25°C, SOIC-8 package | 3 |
| Operating Ambient Temperature Range | TA | -40 | | 150 | °C | Range L (SOIC-8 package) | 3 |
| Junction Temperature | TJ(MAX) | | | 165 | °C | | 3 |
| Storage Temperature Range | Tstg | -65 | | 170 | °C | | 3 |
| Dielectric Surge Strength Test Voltage | VSURGE | | | 6000 | V | Tested ±5 pulses at 2/minute per IEC 61000-4-5, 1.2 µs (rise) / 50 µs (width) | 3 |
| Dielectric Strength Test Voltage | VISO | | | 2400 | VRMS | Agency type-tested for 60 seconds per UL 60950-1 (edition 2) | 3 |
| Working Voltage for Basic Isolation | VWVBI | | | 420 | VPK or VDC | Maximum approved working voltage for basic isolation per UL 60950-1 (edition 2) | 3 |
| Human Body Model ESD | VHBM | -6.5 | | 6.5 | kV | Per AEC-Q100, SOIC-8 package | 3 |
| Charged Device Model ESD | VCDM | -1 | | 1 | kV | Per AEC-Q100 | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | 1500 mm2 of 4 oz. copper (0.1388 mm) connected to pins 1 and 2, | 20 |
## CAD (KiCad official)
- Symbol: `ACS71240LLCBTR-050U5`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `acs71240llcbtr-050u5-etched.step` / `acs71240llcbtr-050u5-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acs71240llcbtr-050u5.step` / `acs71240llcbtr-050u5.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/acs71240llcbtr-050u5-datasheet.pdf) (25 pp, sha256 `bb47820aa99ea699`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/acs71240llcbtr-050u5-datasheet.pdf)