component
ACS711KLCTR-12AB-T
Public Made by Adomby adom
Allegro MicroSystems LLC Current Sensors, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
2 files changed
+267−1
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/acs711klctr-12ab-t-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+265@@ -0,0 +1,265 @@+{+ "schema": "adom.pads/1",+ "slug": "acs711klctr-12ab-t",+ "footprint": "SOIC-8_3.9x4.9mm_P1.27mm",+ "generated_from": {+ "footprint": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.475,+ -1.905+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4"+ },+ "pad_count": 8,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "IP+",+ "type": "passive",+ "description": "Primary current sense terminal (positive). Pins 1 and 2 are internally fused and form one side of the ~1.2 mΩ internal current-sensing conductor. Rated for 100 VAC/VDC working isolation to pins 5-8.",+ "is_pin1": true,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "IP+",+ "type": "passive",+ "description": "Primary current sense terminal (positive). Tied internally to pin 1; both must be connected in parallel to carry the primary current.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "IP-",+ "type": "passive",+ "description": "Primary current sense terminal (negative/return). Pins 3 and 4 are internally fused and form the return side of the internal ~1.2 mΩ conduction path.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "IP-",+ "type": "passive",+ "description": "Primary current sense terminal (negative/return). Tied internally to pin 3; both must be connected in parallel to carry the primary current.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground terminal. Reference for VCC, VIOUT, and FAULT.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "6",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "6",+ "name": "FAULT",+ "type": "output",+ "description": "Overcurrent fault output; active low, open-drain. Latches low when |IP| exceeds ±100% of full-scale (±12.5 A for the -12AB variant) with tFAULT ≈ 1.3 µs. Requires an external pull-up resistor (RPU ≥ 1 kΩ) to VCC; VOL ≤ 0.3 V with RPU = 1 kΩ. Reset only by a power-off/on cycle with VCC held below 200 mV for ≥100 µs.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "7",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "7",+ "name": "VIOUT",+ "type": "output",+ "description": "Analog output signal. Ratiometric voltage proportional to primary current IP with 110 mV/A sensitivity centered at VCC/2 for IP = 0 A. VIOH = VCC-0.3 V max, VIOL = 0.3 V max; drives up to 1 nF load; 100 kHz bandwidth, 4.6 µs response time.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "8",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "8",+ "name": "VCC",+ "type": "power_in",+ "description": "Device power supply terminal. 3 V to 5.5 V (3.3 V nominal for rated accuracy). Supply current ICC ≈ 4 mA typ (5.5 mA max). Bypass with 0.1 µF ceramic to GND.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}