component
ACS710KLATR-6BB-NL-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Current Sensors, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownACS710KLATR-6BB-NL-T
Allegro MicroSystems, LLC · Current Sensors · SOIC-16-300mil
ACS710KLATR-6BB-NL-T from Allegro MicroSystems, LLC, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Sensed current copper conduction path terminal, fused internally with pins 2-4 and looped to the IP- pins; supports unidirectional or bidirectional current flow (primary resistance typ. 1 mΩ). |
| 2 | IP+ | passive | Sensed current copper conduction path terminal, fused internally with pins 1, 3, 4 and looped to the IP- pins; supports unidirectional or bidirectional current flow. |
| 3 | IP+ | passive | Sensed current copper conduction path terminal, fused internally with pins 1, 2, 4 and looped to the IP- pins; supports unidirectional or bidirectional current flow. |
| 4 | IP+ | passive | Sensed current copper conduction path terminal, fused internally with pins 1-3 and looped to the IP- pins; supports unidirectional or bidirectional current flow. |
| 5 | IP- | passive | Sensed current copper conduction path terminal, fused internally with pins 6-8 and looped to the IP+ pins; supports unidirectional or bidirectional current flow. |
| 6 | IP- | passive | Sensed current copper conduction path terminal, fused internally with pins 5, 7, 8 and looped to the IP+ pins; supports unidirectional or bidirectional current flow. |
| 7 | IP- | passive | Sensed current copper conduction path terminal, fused internally with pins 5, 6, 8 and looped to the IP+ pins; supports unidirectional or bidirectional current flow. |
| 8 | IP- | passive | Sensed current copper conduction path terminal, fused internally with pins 5-7 and looped to the IP+ pins; supports unidirectional or bidirectional current flow. |
| 9 | GND | power_in | Device ground connection. |
| 10 | VZCR | output | Zero-current (0 A) voltage reference output that scales with VCC (0.5×VCC typ., not a highly accurate reference; 3 mA source and 50 µA sink minimum load capability). |
| 11 | FILTER | passive | Terminal for an external capacitor to GND that sets the device bandwidth (internal RF(INT) typ. 1.7 kΩ; 120 kHz bandwidth with no capacitor). |
| 12 | VIOUT | output | Analog output voltage proportional to the current flowing between the IP+ and IP- pins; load must be ≥10 kΩ and ≤10 nF to GND. |
| 13 | FAULT | output | Active-low overcurrent fault output that goes low when the current between IP+ and IP- exceeds the fault threshold (VFAULT max 0.4 V at 1 mA sink); non-latching version releases when current falls back below threshold. |
| 14 | VCC | power_in | Supply voltage, 3 to 5.5 V (5 V nominal). |
| 15 | VOC | input | Analog input that sets the overcurrent fault threshold, to be set between VCC×0.25 and VCC×0.4 (input resistance min. 2 MΩ). |
| 16 | FAULT_EN | input | Enables overcurrent faulting when high (VIH min 0.8×VCC, VIL max 0.1×VCC, input resistance typ. 1 MΩ). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-16-300mil |
| Category | Sensors |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 3 | 5.5 | V | 7 | ||
| Output Capacitance Load | CLOAD | 10 | nF | VIOUT pin to GND | 7 | ||
| Output Resistive Load | RLOAD | 10 | kΩ | VIOUT pin to GND | 7 | ||
| Supply Current | ICC | 11 | 14.5 | mA | VIOUT open, FAULT pin high | 7 | |
| Full Range Linearity | ELIN | -0.75 | 0.25 | 0.75 | % | IP = ±IP0A | 7 |
| Symmetry | ESYM | 99.1 | 100 | 100.9 | % | IP = ±IP0A | 7 |
| Setting Voltage for Overcurrent Switchpoint | VOC | 0.25 | 0.4 | V | Printed as VCC × 0.25 min and VCC × 0.4 max (multipliers of VCC) | 7 | |
| Overcurrent FAULT Pin Output Voltage | VFAULT | 0.4 | V | 1 mA sink current at FAULT pin | 7 | ||
| FAULT_EN Input Low Voltage Threshold | VIL | 0.1 | V | Printed as 0.1×VCC (multiplier of VCC) | 7 | ||
| FAULT_EN Input High Voltage Threshold | VIH | 0.8 | V | Printed as 0.8 × VCC (multiplier of VCC) | 7 | ||
| Overcurrent Input Pin Resistance | ROC | 2 | MΩ | TA = 25°C, VOC pin to GND | 8 | ||
| Voltage Reference Output | VZCR | 0.48 | 0.5 | 0.51 | V | TA = 25 °C; printed as 0.48 x VCC, 0.5 × VCC, 0.51xVCC (multipliers of VCC) | 8 |
| Voltage Reference Output Load Current (source) | IZCR | 3 | mA | Source current | 8 | ||
| Voltage Reference Output Load Current (sink) | IZCR | 50 | µA | Sink current | 8 | ||
| Optimized Accuracy Range | IPOA | -7.5 | 7.5 | A | X6BB | 9 | |
| Linear Sensing Range | IR | -14 | 14 | A | X6BB | 9 | |
| Supply Voltage (abs max) | VCC | 8 | V | 4 | |||
| Filter Pin Voltage (abs max) | VFILTER | 8 | V | 4 | |||
| Analog Output Pin Voltage (abs max) | VIOUT | 32 | V | 4 | |||
| Overcurrent Input Pin Voltage (abs max) | VOC | 8 | V | 4 | |||
| Overcurrent FAULT Pin Voltage (abs max) | VFAULT | 8 | V | 4 | |||
| Fault Enable Pin Voltage (abs max) | VFAULTEN | 8 | V | 4 | |||
| Voltage Reference Output Pin Voltage (abs max) | VZCR | 8 | V | 4 | |||
| DC Reverse Voltage | VRdcx | -0.5 | V | VCC, FILTER, VIOUT, VOC, FAULT, FAULT_EN, and VZCR pins | 4 | ||
| Excess to Supply Voltage | VEX | 0.3 | V | Voltage by which pin voltage can exceed the VCC pin voltage | 4 | ||
| Output Current Source | IIOUT(Source) | 3 | mA | 4 | |||
| Output Current Sink | IIOUT(Sink) | 1 | mA | 4 | |||
| Operating Ambient Temperature | TA | -40 | 125 | °C | Range K | 4 | |
| Junction Temperature | TJ(max) | 165 | °C | 4 | |||
| Storage Temperature | Tstg | -65 | 170 | °C | 4 | ||
| Package Thermal Resistance | RθJA | 17 | ºC/W | Mounted on Allegro demo board with 1332 mm2 of 2 oz. copper connected to the primary leadframe, with thermal vias | 4 | ||
| Dielectric Surge Strength Test Voltage | VSURGE | 6000 | V | Tested ±5 pulses at 2/minute per IEC 61000-4-5, 1.2 µs (rise) / 50 µs (width) | 4 | ||
| Dielectric Strength Test Voltage (IEC/UL 60950-1) | VISO | 3600 | VRMS | Agency type-tested for 60 seconds per IEC/UL 60950-1 (2nd Edition) | 4 | ||
| Dielectric Strength Test Voltage (UL 1577) | VISO | 3000 | VRMS | Agency type-tested for 60 seconds per UL 1577 | 4 | ||
| Working Voltage for Basic Isolation | VWVBI | 870 | VPK or VDC | Maximum approved working voltage for basic isolation per IEC/UL 60950-1 (2nd Edition) | 4 | ||
| Nominal Supply Voltage | VCCN | 5 | V | 7 | |||
| Internal Filter Resistance | RF(INT) | 1.7 | kΩ | 7 | |||
| Primary Conductor Resistance | RPRIMARY | 1 | mΩ | TA = 25°C | 7 | ||
| Sensitivity | Sens | 151 | mV/A | IP = 6.5 A, TA = 25°C | 9 | ||
| Electrical Offset Voltage Variation | VOE | 10 | mV | IP = 0 A, TA = 25°C; printed as ±10 | 9 | ||
| Total Output Error | ETOT | 1.6 | % | Over full scale of IPOA, IP applied for 5 ms, TA = 25°C to 125°C; printed as ±1.6 | 9 | ||
| Total Output Error | ETOT | 5.6 | % | Over full scale of IPOA, IP applied for 5 ms, TA =, 40°C to 25°C; printed as ±5.6 | 9 | ||
| Overcurrent Fault Switchpoint Error | EOC | 5 | % | Switchpoint in VOC safe operating area; assumes INCOMP = 0 A; printed as ±5 | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 1,2,3,4 IP+ Sensed current copper conduction path pins. Terminals for current being sensed; | 5 |
CAD (KiCad official)
- Symbol:
ACS710KLATR-6BB-NL-T - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
acs710klatr-6bb-nl-t-etched.step/acs710klatr-6bb-nl-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs710klatr-6bb-nl-t.step/acs710klatr-6bb-nl-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (24 pp, sha256
601c2523d8411c10, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).