component
ACS37800KMACTR-030B3-SPI
Public Made by Adomby adom
Allegro MicroSystems, LLC Monitors & Reset Circuits, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
ACS37800KMACTR-030B3-SPI
Allegro MicroSystems, LLC · Monitors & Reset Circuits · SOIC-16
ACS37800KMACTR-030B3-SPI from Allegro MicroSystems, LLC, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for the current being sensed; fused internally. |
| 2 | IP+ | passive | Terminal for the current being sensed; fused internally. |
| 3 | IP+ | passive | Terminal for the current being sensed; fused internally. |
| 4 | IP+ | passive | Terminal for the current being sensed; fused internally. |
| 5 | IP- | passive | Terminal for the current being sensed; fused internally. |
| 6 | IP- | passive | Terminal for the current being sensed; fused internally. |
| 7 | IP- | passive | Terminal for the current being sensed; fused internally. |
| 8 | IP- | passive | Terminal for the current being sensed; fused internally. |
| 9 | DIO_1/CS | bidirectional | Digital I/O 1, used as Chip Select (CS) in SPI mode. |
| 10 | DIO_0/MOSI | bidirectional | Digital I/O 0, used as MOSI in SPI mode. |
| 11 | SCL/SCLK | input | Serial clock line, used as SCLK in SPI mode. |
| 12 | SDA/MISO | bidirectional | Serial data line, used as MISO in SPI mode. |
| 13 | VCC | power_in | Device power supply terminal; 4.5 to 5.5 V for the 5 V variant and 2.97 to 3.63 V for the 3.3 V variant. |
| 14 | GND | power_in | Device ground terminal. |
| 15 | VINN | input | Negative voltage input, which must always be connected to GND. |
| 16 | VINP | input | Positive voltage input; differential input range is ±250 mV. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-16 |
| Category | Power Management |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (3.3 V variant) | VCC | 2.97 | 3.3 | 3.63 | V | 3.3 V variant | 6 |
| Supply Current | ICC | 12 | 15 | mA | VCC(min) ≤ VCC ≤ VCC(max), no load on output pins | 6 | |
| Supply Bypass Capacitor | CBYPASS | 0.1 | µF | VCC to GND recommended | 6 | ||
| Differential Input Range | ΔVINR | -250 | 250 | mV | ΔVIN = VINP, VINN(GND) | 6 | |
| Dynamic Input Frequency | fdyn_in | 35 | 300 | Hz | bypass_n_en = 0 | 6 | |
| ADC Fullscale (voltage channel) | ADCV_FS | -27500 | 27500 | codes | ΔVIN = ±250 mV, VINN= GND | 6 | |
| Voltage Channel Power Supply Error (offset) | PSEV_O | -7 | 7 | codes / %VCC | Ratio of change on VCC to change in offset at DC, 100% ±10% VCC(typ) | 6 | |
| Voltage Channel Power Supply Error (sensitivity) | PSEV_S | -0.1 | 0.1 | % / %VCC | Ratio of change on VCC to change in sensitivity at DC, 100% ±10% VCC(typ) | 6 | |
| Voltage Channel PSRR (offset) | PSRRV_O | 60 | 70 | dB | Ratio of change on VCC to change in offset, 10 Hz to 10 kHz, 10% VCC(pk-pk) | 6 | |
| Voltage Channel PSRR (sensitivity) | PSRRV_S | 60 | 75 | dB | Ratio of change on VCC to change in sensitivity, 10 Hz to 10 kHz, 10% VCC(pk-pk) | 6 | |
| ADC Fullscale (current channel) | ADCI_FS | -27500 | 27500 | codes | IP = IPR(min) or IPR(max) | 6 | |
| Current Channel Power Supply Error (offset) | PSEI_O | -60 | 60 | codes / %VCC | Ratio of change on VCC to change in offset at DC, 100% ±10% VCC(typ) | 6 | |
| Current Channel Power Supply Error (sensitivity) | PSEI_S | -0.3 | 0.3 | % / %VCC | Ratio of change on VCC to change in sensitivity at DC, 100% ±10% VCC(typ) | 6 | |
| Current Channel PSRR (offset) | PSRRI_O | 60 | 65 | dB | Ratio of change on VCC to change in offset, 10 Hz to 10 kHz, 10% VCC(pk-pk) | 6 | |
| Current Channel PSRR (sensitivity) | PSRRI_S | 20 | 40 | dB | Ratio of change on VCC to change in sensitivity, 10 Hz to 10 kHz, 10% VCC(pk-pk) | 6 | |
| Fault Range | IFAULT | 0.65 | 2 | × FS | Set using fault field in EEPROM | 7 | |
| DIO Output High Level | VOH(DIO) | 3 | V | VCC = 3.3 V | 7 | ||
| DIO Output Low Level | VOL(DIO) | 0.3 | V | VCC = 3.3 V | 7 | ||
| Digital Input High Voltage | VIH | 2.8 | 3.63 | V | MOSI, SCLK, CS pins, VCC = 3.3 V | 12 | |
| Digital Input Low Voltage | VIL | 0.5 | V | MOSI, SCLK, CS pins | 12 | ||
| SPI Output High Voltage | VOH | 2.8 | 3.3 | 3.8 | V | MISO pin, CL = 20 pF, TA = 25°C, VCC(typ) = 3.3 V | 12 |
| SPI Output Low Voltage | VOL | 0.3 | 0.5 | V | MISO pin, CL = 20 pF, TA = 25°C | 12 | |
| SPI Clock Frequency | fSCLK | 0.1 | 10 | MHz | MISO pin, CL = 20 pF | 12 | |
| SPI Frame Rate | tSPI | 5.8 | 588 | kHz | 12 | ||
| Chip Select to First SCLK Edge | tCS | 50 | ns | Time from CS going low to SCLK falling edge | 12 | ||
| MOSI Setup Time | tSU | 25 | ns | Input setup time before SCLK rising edge | 12 | ||
| MOSI Hold Time | tHD | 50 | ns | Input hold time after SCLK rising edge | 12 | ||
| SCLK to CS Hold Time | tCHD | 5 | ns | Hold SCLK high time before CS rising edge | 12 | ||
| Load Capacitance | CL | 20 | pF | Loading on digital output (MISO) pin | 12 | ||
| Supply Voltage | VCC | 6.5 | V | 3 | |||
| Reverse Supply Voltage | VRCC | -0.5 | V | 3 | |||
| Reverse Input Voltage | VRNP, VRNN | -0.5 | V | 3 | |||
| Digital I/O Voltage | VDIO | 6 | V | SPI, I2C, and general purpose I/O | 3 | ||
| Reverse Digital I/O Voltage | VRDIO | -0.5 | V | 3 | |||
| Maximum Continuous Current | ICMAX | 60 | A | TA = 25°C | 3 | ||
| Operating Ambient Temperature Range K | TA | -40 | 125 | °C | Range K | 3 | |
| Junction Temperature | TJ(max) | 165 | °C | 3 | |||
| Storage Temperature | Tstg | -65 | 170 | °C | 3 | ||
| Package Thermal Resistance (Junction to Ambient) | RθJA | 23 | °C/W | Mounted on ASEK37800 evaluation board, 750 mm2 of 4 oz. copper on each side | 3 | ||
| Package Thermal Resistance (Junction to Lead) | RθJL | 5 | °C/W | Mounted on ACS37800 evaluation board | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, | 3 |
CAD (KiCad official)
- Symbol:
ACS37800KMACTR-030B3-SPI - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
acs37800kmactr-030b3-spi-etched.step/acs37800kmactr-030b3-spi-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs37800kmactr-030b3-spi.step/acs37800kmactr-030b3-spi.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (41 pp, sha256
2ab39f4c8c95831c, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ACS37800KMACTR-030B3-SPI
**Allegro MicroSystems, LLC** · Monitors & Reset Circuits · SOIC-16
ACS37800KMACTR-030B3-SPI from Allegro MicroSystems, LLC, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for the current being sensed; fused internally. |
| 2 | IP+ | passive | Terminal for the current being sensed; fused internally. |
| 3 | IP+ | passive | Terminal for the current being sensed; fused internally. |
| 4 | IP+ | passive | Terminal for the current being sensed; fused internally. |
| 5 | IP- | passive | Terminal for the current being sensed; fused internally. |
| 6 | IP- | passive | Terminal for the current being sensed; fused internally. |
| 7 | IP- | passive | Terminal for the current being sensed; fused internally. |
| 8 | IP- | passive | Terminal for the current being sensed; fused internally. |
| 9 | DIO_1/CS | bidirectional | Digital I/O 1, used as Chip Select (CS) in SPI mode. |
| 10 | DIO_0/MOSI | bidirectional | Digital I/O 0, used as MOSI in SPI mode. |
| 11 | SCL/SCLK | input | Serial clock line, used as SCLK in SPI mode. |
| 12 | SDA/MISO | bidirectional | Serial data line, used as MISO in SPI mode. |
| 13 | VCC | power_in | Device power supply terminal; 4.5 to 5.5 V for the 5 V variant and 2.97 to 3.63 V for the 3.3 V variant. |
| 14 | GND | power_in | Device ground terminal. |
| 15 | VINN | input | Negative voltage input, which must always be connected to GND. |
| 16 | VINP | input | Positive voltage input; differential input range is ±250 mV. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-16 |
| Category | Power Management |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (3.3 V variant) | VCC | 2.97 | 3.3 | 3.63 | V | 3.3 V variant | 6 |
| Supply Current | ICC | | 12 | 15 | mA | VCC(min) ≤ VCC ≤ VCC(max), no load on output pins | 6 |
| Supply Bypass Capacitor | CBYPASS | 0.1 | | | µF | VCC to GND recommended | 6 |
| Differential Input Range | ΔVINR | -250 | | 250 | mV | ΔVIN = VINP, VINN(GND) | 6 |
| Dynamic Input Frequency | fdyn_in | 35 | | 300 | Hz | bypass_n_en = 0 | 6 |
| ADC Fullscale (voltage channel) | ADCV_FS | -27500 | | 27500 | codes | ΔVIN = ±250 mV, VINN= GND | 6 |
| Voltage Channel Power Supply Error (offset) | PSEV_O | -7 | | 7 | codes / %VCC | Ratio of change on VCC to change in offset at DC, 100% ±10% VCC(typ) | 6 |
| Voltage Channel Power Supply Error (sensitivity) | PSEV_S | -0.1 | | 0.1 | % / %VCC | Ratio of change on VCC to change in sensitivity at DC, 100% ±10% VCC(typ) | 6 |
| Voltage Channel PSRR (offset) | PSRRV_O | 60 | 70 | | dB | Ratio of change on VCC to change in offset, 10 Hz to 10 kHz, 10% VCC(pk-pk) | 6 |
| Voltage Channel PSRR (sensitivity) | PSRRV_S | 60 | 75 | | dB | Ratio of change on VCC to change in sensitivity, 10 Hz to 10 kHz, 10% VCC(pk-pk) | 6 |
| ADC Fullscale (current channel) | ADCI_FS | -27500 | | 27500 | codes | IP = IPR(min) or IPR(max) | 6 |
| Current Channel Power Supply Error (offset) | PSEI_O | -60 | | 60 | codes / %VCC | Ratio of change on VCC to change in offset at DC, 100% ±10% VCC(typ) | 6 |
| Current Channel Power Supply Error (sensitivity) | PSEI_S | -0.3 | | 0.3 | % / %VCC | Ratio of change on VCC to change in sensitivity at DC, 100% ±10% VCC(typ) | 6 |
| Current Channel PSRR (offset) | PSRRI_O | 60 | 65 | | dB | Ratio of change on VCC to change in offset, 10 Hz to 10 kHz, 10% VCC(pk-pk) | 6 |
| Current Channel PSRR (sensitivity) | PSRRI_S | 20 | 40 | | dB | Ratio of change on VCC to change in sensitivity, 10 Hz to 10 kHz, 10% VCC(pk-pk) | 6 |
| Fault Range | IFAULT | 0.65 | | 2 | × FS | Set using fault field in EEPROM | 7 |
| DIO Output High Level | VOH(DIO) | 3 | | | V | VCC = 3.3 V | 7 |
| DIO Output Low Level | VOL(DIO) | | | 0.3 | V | VCC = 3.3 V | 7 |
| Digital Input High Voltage | VIH | 2.8 | | 3.63 | V | MOSI, SCLK, CS pins, VCC = 3.3 V | 12 |
| Digital Input Low Voltage | VIL | | | 0.5 | V | MOSI, SCLK, CS pins | 12 |
| SPI Output High Voltage | VOH | 2.8 | 3.3 | 3.8 | V | MISO pin, CL = 20 pF, TA = 25°C, VCC(typ) = 3.3 V | 12 |
| SPI Output Low Voltage | VOL | | 0.3 | 0.5 | V | MISO pin, CL = 20 pF, TA = 25°C | 12 |
| SPI Clock Frequency | fSCLK | 0.1 | | 10 | MHz | MISO pin, CL = 20 pF | 12 |
| SPI Frame Rate | tSPI | 5.8 | | 588 | kHz | | 12 |
| Chip Select to First SCLK Edge | tCS | 50 | | | ns | Time from CS going low to SCLK falling edge | 12 |
| MOSI Setup Time | tSU | 25 | | | ns | Input setup time before SCLK rising edge | 12 |
| MOSI Hold Time | tHD | 50 | | | ns | Input hold time after SCLK rising edge | 12 |
| SCLK to CS Hold Time | tCHD | 5 | | | ns | Hold SCLK high time before CS rising edge | 12 |
| Load Capacitance | CL | | | 20 | pF | Loading on digital output (MISO) pin | 12 |
| Supply Voltage | VCC | | | 6.5 | V | | 3 |
| Reverse Supply Voltage | VRCC | -0.5 | | | V | | 3 |
| Reverse Input Voltage | VRNP, VRNN | -0.5 | | | V | | 3 |
| Digital I/O Voltage | VDIO | | | 6 | V | SPI, I2C, and general purpose I/O | 3 |
| Reverse Digital I/O Voltage | VRDIO | -0.5 | | | V | | 3 |
| Maximum Continuous Current | ICMAX | | | 60 | A | TA = 25°C | 3 |
| Operating Ambient Temperature Range K | TA | -40 | | 125 | °C | Range K | 3 |
| Junction Temperature | TJ(max) | | | 165 | °C | | 3 |
| Storage Temperature | Tstg | -65 | | 170 | °C | | 3 |
| Package Thermal Resistance (Junction to Ambient) | RθJA | | 23 | | °C/W | Mounted on ASEK37800 evaluation board, 750 mm2 of 4 oz. copper on each side | 3 |
| Package Thermal Resistance (Junction to Lead) | RθJL | | 5 | | °C/W | Mounted on ACS37800 evaluation board | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, | 3 |
## CAD (KiCad official)
- Symbol: `ACS37800KMACTR-030B3-SPI`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `acs37800kmactr-030b3-spi-etched.step` / `acs37800kmactr-030b3-spi-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acs37800kmactr-030b3-spi.step` / `acs37800kmactr-030b3-spi.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/acs37800kmactr-030b3-spi-datasheet.pdf) (41 pp, sha256 `2ab39f4c8c95831c`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/acs37800kmactr-030b3-spi-datasheet.pdf)