ACPL-M50L-500E

{
  "slug": "acpl-m50l-500e",
  "version": "0.1.0",
  "type": "component",
  "description": "Broadcom AVAGO Logic Output Optoisolators, SOP-5-175mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "optoisolators",
    "acpl-m50l-500e",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "acpl-m50l-500e.kicad_sym",
    "acpl-m50l-500e.kicad_mod",
    "acpl-m50l-500e.glb",
    "acpl-m50l-500e.step",
    "acpl-m50l-500e.lbr",
    "docs/hero.png",
    "docs/acpl-m50l-500e-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "acpl-m50l-500e-hero.glb",
    "acpl-m50l-500e-hero.overlay.json",
    "acpl-m50l-500e-etched.glb"
  ],
  "component": {
    "mpn": "ACPL-M50L-500E",
    "manufacturer": "Broadcom AVAGO",
    "package": "SOP-5-175mil",
    "pin_count": 5,
    "category": "Optoisolators",
    "subcategory": "Logic Output Optoisolators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881738374524928",
    "parts": {
      "symbol": "acpl-m50l-500e.kicad_sym",
      "footprint": "acpl-m50l-500e.kicad_mod",
      "model_3d": "acpl-m50l-500e-hero.glb",
      "model_3d_plain": "acpl-m50l-500e-etched.glb",
      "model_3d_step": "acpl-m50l-500e-etched.step",
      "model_3d_step_plain": "acpl-m50l-500e.step",
      "lbr": "acpl-m50l-500e.lbr"
    },
    "distributor_links": {
      "lcsc": "C54677",
      "digikey": "516-2909-2-ND",
      "mouser": "630-ACPL-M50L-500E"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T06:10:26Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "516-2909-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "630-ACPL-M50L-500E",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "ANODE",
        "type": "input",
        "description": "LED anode input; the LED forward input current is specified at IF = 3 mA, with a 10 mA IFH maximum and 5 V reverse voltage rating (VR)."
      },
      {
        "number": "3",
        "name": "CATHODE",
        "type": "passive",
        "description": "LED cathode, returned to the input side; the input is shorted internally to pin 1 for the two-terminal input (reverse voltage limit 5 V)."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the output transistor and detector; recommended 0.1 µF bypass capacitor between pins 4 and 6."
      },
      {
        "number": "5",
        "name": "VO",
        "type": "output",
        "description": "Open-collector output, TTL compatible; logic low when the LED is on (IF = 3 mA), absolute maximum output voltage -0.5 V to 24 V and average output current 8 mA."
      },
      {
        "number": "6",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, 2.7 V to 24 V recommended (30 V absolute maximum); bypass with 0.1 µF to GND on pin 4."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The SO-5 package is numbered 1, 3, 4, 5, 6 with no pin 2 printed on the package; pin 2 is omitted be; Pin 1 vs pin 3 assignment (Anode on 1, Cathode on 3) is inferred from the page 1 pin-number list '5 ; The datasheet's SO-5 outline and pin-number text is partly jumbled in the extraction; the 'hint' SOP"
        ],
        "pages_sent": 16,
        "cost_usd": 0.0808,
        "at": "2026-10-17T06:10:10"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881738374524928",
        "pages": 16,
        "sha256": "b297ae34bbb0d71b",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 5,
        "described": 5,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.0,
          3.6,
          3.0
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d1bd41d97499dfc385b89d404263467fc2c4460119d6300d6dec626d4e263210",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "acpl-m50l-500e-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          3.6,
          3.0
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "9eb346bb472460f66e850280f5ed671e4ed7bc581e5adf3b850ca2175e948887",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}