ACPL-K342-500E

{
  "slug": "acpl-k342-500e",
  "version": "0.1.0",
  "type": "component",
  "description": "Broadcom AVAGO Logic Output Optoisolators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "optoisolators",
    "acpl-k342-500e",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "acpl-k342-500e.kicad_sym",
    "acpl-k342-500e.kicad_mod",
    "acpl-k342-500e.glb",
    "acpl-k342-500e.step",
    "acpl-k342-500e.lbr",
    "docs/hero.png",
    "docs/acpl-k342-500e-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "acpl-k342-500e-hero.glb",
    "acpl-k342-500e-hero.overlay.json",
    "acpl-k342-500e-etched.glb"
  ],
  "component": {
    "mpn": "ACPL-K342-500E",
    "manufacturer": "Broadcom AVAGO",
    "package": "SO-8",
    "pin_count": 8,
    "category": "Optoisolators",
    "subcategory": "Logic Output Optoisolators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588917619499388928",
    "parts": {
      "symbol": "acpl-k342-500e.kicad_sym",
      "footprint": "acpl-k342-500e.kicad_mod",
      "model_3d": "acpl-k342-500e-hero.glb",
      "model_3d_plain": "acpl-k342-500e-etched.glb",
      "model_3d_step": "acpl-k342-500e-etched.step",
      "model_3d_step_plain": "acpl-k342-500e.step",
      "lbr": "acpl-k342-500e.lbr"
    },
    "distributor_links": {
      "lcsc": "C691948"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T11:44:44Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect pin on the input side of the Stretched SO-8 package."
      },
      {
        "number": "2",
        "name": "ANODE",
        "type": "input",
        "description": "LED anode; recommended LED on-current IF(ON) is 7 mA to 16 mA, with 5 V maximum reverse voltage."
      },
      {
        "number": "3",
        "name": "CATHODE",
        "type": "input",
        "description": "LED cathode; the LED is off when VF(OFF) is between -3.6 V and 0.8 V."
      },
      {
        "number": "4",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect pin on the input side of the Stretched SO-8 package."
      },
      {
        "number": "5",
        "name": "VEE",
        "type": "power_in",
        "description": "Negative output supply (ground reference); a 1 uF bypass capacitor must be connected between VCC and VEE."
      },
      {
        "number": "6",
        "name": "VCLAMP",
        "type": "output",
        "description": "Active Miller clamp output that activates when the gate voltage falls below 2.3 V relative to VEE, sinking up to 2.5 A peak; connect to VEE when not in use."
      },
      {
        "number": "7",
        "name": "VOUT",
        "type": "output",
        "description": "Rail-to-rail gate drive output with 2.5 A maximum peak output current."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive output supply, 15 V to 30 V (VCC-VEE) recommended with 35 V absolute maximum, and a 1 uF bypass capacitor to VEE."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers and names were read from the figure label text on page 2 and cross-checked against the a; VCLAMP is typed as passive because the datasheet gives no formal pin type; it senses gate voltage an; LED pins are typed passive by convention for an optocoupler input; the datasheet does not assign an "
        ],
        "pages_sent": 24,
        "cost_usd": 0.112,
        "at": "2026-10-18T11:41:48"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588917619499388928",
        "pages": 24,
        "sha256": "ba5bcfc02dd3c7f3",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "acpl-k342-500e.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "acpl-k342-500e-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "1c2636d4809f0afc5af4cb96f8984a2d8f46a9108e4c737af5f925db1b4c9e16",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}