component
ACPL-K342-500E
Public Made by Adomby adom
Broadcom AVAGO Logic Output Optoisolators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ACPL-K342-500E
Broadcom AVAGO · Logic Output Optoisolators · SO-8
ACPL-K342-500E from Broadcom AVAGO, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect pin on the input side of the Stretched SO-8 package. |
| 2 | ANODE | input | LED anode; recommended LED on-current IF(ON) is 7 mA to 16 mA, with 5 V maximum reverse voltage. |
| 3 | CATHODE | input | LED cathode; the LED is off when VF(OFF) is between -3.6 V and 0.8 V. |
| 4 | NC | unconnected | No connect pin on the input side of the Stretched SO-8 package. |
| 5 | VEE | power_in | Negative output supply (ground reference); a 1 uF bypass capacitor must be connected between VCC and VEE. |
| 6 | VCLAMP | output | Active Miller clamp output that activates when the gate voltage falls below 2.3 V relative to VEE, sinking up to 2.5 A peak; connect to VEE when not in use. |
| 7 | VOUT | output | Rail-to-rail gate drive output with 2.5 A maximum peak output current. |
| 8 | VCC | power_in | Positive output supply, 15 V to 30 V (VCC-VEE) recommended with 35 V absolute maximum, and a 1 uF bypass capacitor to VEE. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SO-8 |
| Category | Optoisolators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TS | -55 | 125 | °C | 7 | ||
| Operating Temperature | TA | -40 | 105 | °C | 7 | ||
| Output IC Junction Temperature | TJ | 125 | °C | 7 | |||
| Average Input Current | IF(AVG) | 25 | mA | Derate linearly above 70°C free-air temperature at 0.3 mA/°C | 7 | ||
| Peak Transient Input Current | IF(TRAN) | 1 | A | <1 ms pulse width, 300 pps | 7 | ||
| Reverse Input Voltage | VR | 5 | V | 7 | |||
| High Peak Output Current | IOH(PEAK) | 2.5 | A | Maximum pulse width = 10 μs | 7 | ||
| Low Peak Output Current | IOL(PEAK) | 2.5 | A | Maximum pulse width = 10 μs | 7 | ||
| Peak Clamp Sink Current | ICLAMP | 2.5 | A | Maximum pulse width = 10 μs | 7 | ||
| Total Output Supply Voltage | VCC, VEE | 0 | 35 | V | 7 | ||
| Output Voltage | VO(PEAK) | -0.5 | V | Maximum is VCC (printed as VCC, not a number) | 7 | ||
| Output IC Power Dissipation | PO | 500 | mW | Derate linearly above 85°C free-air temperature at 12.5 mW/°C | 7 | ||
| Total Power Dissipation | PT | 550 | mW | Derate linearly above 85°C free-air temperature at 13.75 mW/°C; LED junction temperature not to exceed 125°C | 7 | ||
| Lead Solder Temperature | 260 | °C | 10 s, 1.6 mm below seating plane | 7 | |||
| Operating Temperature | TA | -40 | 105 | °C | 7 | ||
| Output Supply Voltage | VCC, VEE | 15 | 30 | V | 7 | ||
| Input Current (ON) | IF(ON) | 7 | 16 | mA | 7 | ||
| Input Voltage (OFF) | VF(OFF) | -3.6 | 0.8 | V | 7 | ||
| High Level Peak Output Current | IOH | -0.5 | -1.2 | A | VO = VCC, 4V; maximum pulse width = 50 μs | 8 | |
| High Level Peak Output Current | IOH | -2 | A | VO = VCC, 15V; maximum pulse width = 10 μs | 8 | ||
| Low Level Peak Output Current | IOL | 0.5 | 2.7 | A | VO = VEE + 2.5V; maximum pulse width = 50 μs | 8 | |
| Low Level Peak Output Current | IOL | 2 | A | VO = VEE + 15V; maximum pulse width = 10 μs | 8 | ||
| High Output Transistor RDS(ON) | RDS,OH | 2.6 | 5 | Ω | IOH = -2.0A | 8 | |
| Low Output Transistor RDS(ON) | RDS,OL | 0.8 | 2 | Ω | IOL = 2.0A | 8 | |
| Clamp Output Peak Current | ICLAMP | 1 | 2.5 | A | VO = VEE + 2.5V; maximum pulse width = 10 μs | 8 | |
| Clamp Output Transistor RDS(ON) | RDS,CLAMP | 0.8 | 2 | Ω | ICLAMP = 1.5A | 8 | |
| Low Level Output Voltage | VOL | 0.07 | 0.25 | V | IO = 100 mA | 8 | |
| High Level Supply Current | ICCH | 1.68 | 2.5 | mA | Rg = 10Ω, Cg = 25 nF, IF = 10 mA | 8 | |
| Low Level Supply Current | ICCL | 2 | 2.5 | mA | Rg = 10Ω, Cg = 25 nF, IF = 0 mA | 8 | |
| Threshold Input Current Low to High | IFLH | 0.5 | 1.5 | 4 | mA | Rg = 10Ω, Cg = 25 nF, VO > 5V | 8 |
| Threshold Input Voltage High to Low | VFHL | 0.8 | V | 8 | |||
| Input Forward Voltage | VF | 1.2 | 1.55 | 1.95 | V | IF = 10 mA | 8 |
| Input Reverse Breakdown Voltage | BVR | 5 | V | IR = 100 μA | 8 | ||
| UVLO Threshold (positive going) | VUVLO+ | 11 | 12.3 | 13.5 | V | VO > 5V, IF = 10 mA | 8 |
| UVLO Threshold (negative going) | VUVLO- | 9.5 | 10.7 | 12 | V | 8 | |
| Propagation Delay Time to High Output Level | tPLH | 0.1 | 0.26 | 0.35 | μs | Rg = 10Ω, Cg = 25 nF, f = 20 kHz, duty cycle = 50%, IF = 7 mA to 16 mA, VCC = 15V to 30V | 9 |
| Propagation Delay Time to Low Output Level | tPHL | 0.05 | 0.145 | 0.25 | μs | Rg = 10Ω, Cg = 25 nF, f = 20 kHz, duty cycle = 50%, IF = 7 mA to 16 mA, VCC = 15V to 30V | 9 |
| Propagation Delay Difference Between Any Two Parts | PDD (tPHL, tPLH) | -0.01 | -0.1 | -0.2 | μs | Difference between tPHL and tPLH between any two parts under the same test condition | 9 |
| Output High Level Common Mode Transient Immunity | /CMH/ | 40 | 50 | kV/μs | TA = 25 °C, IF = 10 mA, VCC = 30V, VCM = 1500V with split resistors | 9 | |
| Output High Level Common Mode Transient Immunity | /CMH/ | 25 | 35 | kV/μs | TA = 25 °C, IF = 10 mA, VCC = 30V, VCM = 1000V without split resistors | 9 | |
| Output Low Level Common Mode Transient Immunity | /CML/ | 40 | 50 | kV/μs | TA = 25 °C, VF = 0V, VCC = 30V, VCM = 1500V with split resistors | 9 | |
| Output Low Level Common Mode Transient Immunity | /CML/ | 25 | 35 | kV/μs | TA = 25 °C, VF = 0V, VCC = 30V, VCM = 1000V without split resistors | 9 | |
| Input-Output Momentary Withstand Voltage (ACPL-K342) | VISO | 5000 | VRMS | RH < 50%, t = 1 min., TA = 25°C | 10 | ||
| LED-to-Ambient Thermal Resistance | R11 | 145 | °C/W | Thermal model in application notes; device on high conductivity test board per JEDEC 51-7 | 10 | ||
| LED-to-Detector Thermal Resistance | R12 | 25 | °C/W | Thermal model in application notes; device on high conductivity test board per JEDEC 51-7 | 10 | ||
| Detector-to-LED Thermal Resistance | R21 | 38 | °C/W | Thermal model in application notes; device on high conductivity test board per JEDEC 51-7 | 10 | ||
| Detector-to-Ambient Thermal Resistance | R22 | 46 | °C/W | Thermal model in application notes; device on high conductivity test board per JEDEC 51-7 | 10 |
CAD (KiCad official)
- Symbol:
ACPL-K342-500E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
acpl-k342-500e-etched.step/acpl-k342-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acpl-k342-500e.step/acpl-k342-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (24 pp, sha256
ba5bcfc02dd3c7f3, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ACPL-K342-500E
**Broadcom AVAGO** · Logic Output Optoisolators · SO-8
ACPL-K342-500E from Broadcom AVAGO, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect pin on the input side of the Stretched SO-8 package. |
| 2 | ANODE | input | LED anode; recommended LED on-current IF(ON) is 7 mA to 16 mA, with 5 V maximum reverse voltage. |
| 3 | CATHODE | input | LED cathode; the LED is off when VF(OFF) is between -3.6 V and 0.8 V. |
| 4 | NC | unconnected | No connect pin on the input side of the Stretched SO-8 package. |
| 5 | VEE | power_in | Negative output supply (ground reference); a 1 uF bypass capacitor must be connected between VCC and VEE. |
| 6 | VCLAMP | output | Active Miller clamp output that activates when the gate voltage falls below 2.3 V relative to VEE, sinking up to 2.5 A peak; connect to VEE when not in use. |
| 7 | VOUT | output | Rail-to-rail gate drive output with 2.5 A maximum peak output current. |
| 8 | VCC | power_in | Positive output supply, 15 V to 30 V (VCC-VEE) recommended with 35 V absolute maximum, and a 1 uF bypass capacitor to VEE. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SO-8 |
| Category | Optoisolators |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TS | -55 | | 125 | °C | | 7 |
| Operating Temperature | TA | -40 | | 105 | °C | | 7 |
| Output IC Junction Temperature | TJ | | | 125 | °C | | 7 |
| Average Input Current | IF(AVG) | | | 25 | mA | Derate linearly above 70°C free-air temperature at 0.3 mA/°C | 7 |
| Peak Transient Input Current | IF(TRAN) | | | 1 | A | <1 ms pulse width, 300 pps | 7 |
| Reverse Input Voltage | VR | | | 5 | V | | 7 |
| High Peak Output Current | IOH(PEAK) | | | 2.5 | A | Maximum pulse width = 10 μs | 7 |
| Low Peak Output Current | IOL(PEAK) | | | 2.5 | A | Maximum pulse width = 10 μs | 7 |
| Peak Clamp Sink Current | ICLAMP | | | 2.5 | A | Maximum pulse width = 10 μs | 7 |
| Total Output Supply Voltage | VCC, VEE | 0 | | 35 | V | | 7 |
| Output Voltage | VO(PEAK) | -0.5 | | | V | Maximum is VCC (printed as VCC, not a number) | 7 |
| Output IC Power Dissipation | PO | | | 500 | mW | Derate linearly above 85°C free-air temperature at 12.5 mW/°C | 7 |
| Total Power Dissipation | PT | | | 550 | mW | Derate linearly above 85°C free-air temperature at 13.75 mW/°C; LED junction temperature not to exceed 125°C | 7 |
| Lead Solder Temperature | | | | 260 | °C | 10 s, 1.6 mm below seating plane | 7 |
| Operating Temperature | TA | -40 | | 105 | °C | | 7 |
| Output Supply Voltage | VCC, VEE | 15 | | 30 | V | | 7 |
| Input Current (ON) | IF(ON) | 7 | | 16 | mA | | 7 |
| Input Voltage (OFF) | VF(OFF) | -3.6 | | 0.8 | V | | 7 |
| High Level Peak Output Current | IOH | -0.5 | -1.2 | | A | VO = VCC, 4V; maximum pulse width = 50 μs | 8 |
| High Level Peak Output Current | IOH | -2 | | | A | VO = VCC, 15V; maximum pulse width = 10 μs | 8 |
| Low Level Peak Output Current | IOL | 0.5 | 2.7 | | A | VO = VEE + 2.5V; maximum pulse width = 50 μs | 8 |
| Low Level Peak Output Current | IOL | 2 | | | A | VO = VEE + 15V; maximum pulse width = 10 μs | 8 |
| High Output Transistor RDS(ON) | RDS,OH | | 2.6 | 5 | Ω | IOH = -2.0A | 8 |
| Low Output Transistor RDS(ON) | RDS,OL | | 0.8 | 2 | Ω | IOL = 2.0A | 8 |
| Clamp Output Peak Current | ICLAMP | 1 | 2.5 | | A | VO = VEE + 2.5V; maximum pulse width = 10 μs | 8 |
| Clamp Output Transistor RDS(ON) | RDS,CLAMP | | 0.8 | 2 | Ω | ICLAMP = 1.5A | 8 |
| Low Level Output Voltage | VOL | | 0.07 | 0.25 | V | IO = 100 mA | 8 |
| High Level Supply Current | ICCH | | 1.68 | 2.5 | mA | Rg = 10Ω, Cg = 25 nF, IF = 10 mA | 8 |
| Low Level Supply Current | ICCL | | 2 | 2.5 | mA | Rg = 10Ω, Cg = 25 nF, IF = 0 mA | 8 |
| Threshold Input Current Low to High | IFLH | 0.5 | 1.5 | 4 | mA | Rg = 10Ω, Cg = 25 nF, VO > 5V | 8 |
| Threshold Input Voltage High to Low | VFHL | 0.8 | | | V | | 8 |
| Input Forward Voltage | VF | 1.2 | 1.55 | 1.95 | V | IF = 10 mA | 8 |
| Input Reverse Breakdown Voltage | BVR | 5 | | | V | IR = 100 μA | 8 |
| UVLO Threshold (positive going) | VUVLO+ | 11 | 12.3 | 13.5 | V | VO > 5V, IF = 10 mA | 8 |
| UVLO Threshold (negative going) | VUVLO- | 9.5 | 10.7 | 12 | V | | 8 |
| Propagation Delay Time to High Output Level | tPLH | 0.1 | 0.26 | 0.35 | μs | Rg = 10Ω, Cg = 25 nF, f = 20 kHz, duty cycle = 50%, IF = 7 mA to 16 mA, VCC = 15V to 30V | 9 |
| Propagation Delay Time to Low Output Level | tPHL | 0.05 | 0.145 | 0.25 | μs | Rg = 10Ω, Cg = 25 nF, f = 20 kHz, duty cycle = 50%, IF = 7 mA to 16 mA, VCC = 15V to 30V | 9 |
| Propagation Delay Difference Between Any Two Parts | PDD (tPHL, tPLH) | -0.01 | -0.1 | -0.2 | μs | Difference between tPHL and tPLH between any two parts under the same test condition | 9 |
| Output High Level Common Mode Transient Immunity | /CMH/ | 40 | 50 | | kV/μs | TA = 25 °C, IF = 10 mA, VCC = 30V, VCM = 1500V with split resistors | 9 |
| Output High Level Common Mode Transient Immunity | /CMH/ | 25 | 35 | | kV/μs | TA = 25 °C, IF = 10 mA, VCC = 30V, VCM = 1000V without split resistors | 9 |
| Output Low Level Common Mode Transient Immunity | /CML/ | 40 | 50 | | kV/μs | TA = 25 °C, VF = 0V, VCC = 30V, VCM = 1500V with split resistors | 9 |
| Output Low Level Common Mode Transient Immunity | /CML/ | 25 | 35 | | kV/μs | TA = 25 °C, VF = 0V, VCC = 30V, VCM = 1000V without split resistors | 9 |
| Input-Output Momentary Withstand Voltage (ACPL-K342) | VISO | 5000 | | | VRMS | RH < 50%, t = 1 min., TA = 25°C | 10 |
| LED-to-Ambient Thermal Resistance | R11 | | 145 | | °C/W | Thermal model in application notes; device on high conductivity test board per JEDEC 51-7 | 10 |
| LED-to-Detector Thermal Resistance | R12 | | 25 | | °C/W | Thermal model in application notes; device on high conductivity test board per JEDEC 51-7 | 10 |
| Detector-to-LED Thermal Resistance | R21 | | 38 | | °C/W | Thermal model in application notes; device on high conductivity test board per JEDEC 51-7 | 10 |
| Detector-to-Ambient Thermal Resistance | R22 | | 46 | | °C/W | Thermal model in application notes; device on high conductivity test board per JEDEC 51-7 | 10 |
## CAD (KiCad official)
- Symbol: `ACPL-K342-500E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `acpl-k342-500e-etched.step` / `acpl-k342-500e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acpl-k342-500e.step` / `acpl-k342-500e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Broadcom AVAGO datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588917619499388928) (24 pp, sha256 `ba5bcfc02dd3c7f3`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/acpl-k342-500e-datasheet.pdf)