ACPL-C797-500E

{
  "schema_version": 1,
  "type": "component",
  "slug": "acpl-c797-500e",
  "title": "ACPL-C797-500E",
  "brief": "Broadcom AVAGO Logic Output Optoisolators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "optoisolators",
    "acpl-c797-500e",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "ACPL-C797-500E",
    "manufacturer": "Broadcom AVAGO",
    "package": "SO-8",
    "pin_count": 8,
    "category": "Optoisolators",
    "subcategory": "Logic Output Optoisolators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588917230528159744",
    "parts": {
      "symbol": "acpl-c797-500e.kicad_sym",
      "footprint": "acpl-c797-500e.kicad_mod",
      "model_3d": "acpl-c797-500e-hero.glb",
      "model_3d_plain": "acpl-c797-500e.glb",
      "model_3d_step": "acpl-c797-500e-etched.step",
      "model_3d_step_plain": "acpl-c797-500e.step",
      "lbr": "acpl-c797-500e.lbr"
    },
    "distributor_links": {
      "lcsc": "C691942",
      "digikey": "516-4113-2-ND",
      "mouser": "630-ACPL-C797-500E"
    },
    "distributor_check": {
      "checked_at": "2026-10-09T18:25:17Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "516-4113-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "630-ACPL-C797-500E",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD1",
        "type": "power_in",
        "description": "Supply voltage for the signal input (analog) side, relative to GND1, recommended 4.5 V to 5.5 V with absolute maximum supply of 6.0 V."
      },
      {
        "number": "2",
        "name": "VIN+",
        "type": "power_in",
        "description": "Positive analog input with recommended input range ±200 mV (full-scale ±320 mV), and DC voltage up to -2 V does not cause latch-up or damage."
      },
      {
        "number": "3",
        "name": "VIN-",
        "type": "power_in",
        "description": "Negative analog input with recommended input range ±200 mV (full-scale ±320 mV), normally connected to GND1."
      },
      {
        "number": "4",
        "name": "GND1",
        "type": "power_in",
        "description": "Supply ground for the signal input side, which is the reference for VDD1 and the analog inputs."
      },
      {
        "number": "5",
        "name": "GND2",
        "type": "power_in",
        "description": "Supply ground for the data/clock output (digital) side, which is the reference for VDD2."
      },
      {
        "number": "6",
        "name": "MDAT",
        "type": "output",
        "description": "Modulator data output, a 1-bit data stream at 10 MHz with digital output limits of -0.5 V to VDD2 + 0.5 V."
      },
      {
        "number": "7",
        "name": "MCLK",
        "type": "output",
        "description": "Modulator clock output, 9 MHz to 11 MHz (10 MHz typical) with 40% to 60% duty cycle at 15 pF load, with digital output limits of -0.5 V to VDD2 + 0.5 V."
      },
      {
        "number": "8",
        "name": "VDD2",
        "type": "power_in",
        "description": "Supply voltage for the data output (digital) side, relative to GND2, recommended 3 V to 5.5 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Requested package is SO-8; the datasheet only gives the package as Stretched SO-8 (SSO-8). The 8-pin; Pin descriptions are taken from Table 1 on page 2. The electrical limits quoted in the descriptions "
        ],
        "pages_sent": 18,
        "cost_usd": 0.0859,
        "at": "2026-10-09T18:23:05"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588917230528159744",
        "pages": 18,
        "sha256": "4a397abbec5ea019",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "acpl-c797-500e.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-09",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "acpl-c797-500e-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "f50cdf6a9317ad6e73a3942a6edf48510907a70e413dea45013de2de35d5818a",
        "checked": "2026-10-09",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Broadcom AVAGO",
      "Package": "SO-8",
      "Category": "Optoisolators",
      "Pins": "8"
    }
  },
  "variants": [],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "acpl-c797-500e"
  ],
  "discovery_pitch": "ACPL-C797-500E (Broadcom AVAGO) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "acpl-c797-500e.kicad_sym",
    "acpl-c797-500e.kicad_mod",
    "acpl-c797-500e.glb",
    "acpl-c797-500e.step",
    "acpl-c797-500e.lbr",
    "docs/hero.png",
    "docs/acpl-c797-500e-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "acpl-c797-500e-hero.glb",
    "acpl-c797-500e-hero.overlay.json"
  ],
  "visibility": {
    "public": true
  }
}