component
ACPL-C797-500E
Public Made by Adomby adom
Broadcom AVAGO Logic Output Optoisolators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ACPL-C797-500E
Broadcom AVAGO · Logic Output Optoisolators · SO-8
ACPL-C797-500E from Broadcom AVAGO, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for the signal input (analog) side, relative to GND1, recommended 4.5 V to 5.5 V with absolute maximum supply of 6.0 V. |
| 2 | VIN+ | power_in | Positive analog input with recommended input range ±200 mV (full-scale ±320 mV), and DC voltage up to -2 V does not cause latch-up or damage. |
| 3 | VIN- | power_in | Negative analog input with recommended input range ±200 mV (full-scale ±320 mV), normally connected to GND1. |
| 4 | GND1 | power_in | Supply ground for the signal input side, which is the reference for VDD1 and the analog inputs. |
| 5 | GND2 | power_in | Supply ground for the data/clock output (digital) side, which is the reference for VDD2. |
| 6 | MDAT | output | Modulator data output, a 1-bit data stream at 10 MHz with digital output limits of -0.5 V to VDD2 + 0.5 V. |
| 7 | MCLK | output | Modulator clock output, 9 MHz to 11 MHz (10 MHz typical) with 40% to 60% duty cycle at 15 pF load, with digital output limits of -0.5 V to VDD2 + 0.5 V. |
| 8 | VDD2 | power_in | Supply voltage for the data output (digital) side, relative to GND2, recommended 3 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SO-8 |
| Category | Optoisolators |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
ACPL-C797-500E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
acpl-c797-500e-etched.step/acpl-c797-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acpl-c797-500e.step/acpl-c797-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (18 pp, sha256
4a397abbec5ea019, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ACPL-C797-500E
**Broadcom AVAGO** · Logic Output Optoisolators · SO-8
ACPL-C797-500E from Broadcom AVAGO, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for the signal input (analog) side, relative to GND1, recommended 4.5 V to 5.5 V with absolute maximum supply of 6.0 V. |
| 2 | VIN+ | power_in | Positive analog input with recommended input range ±200 mV (full-scale ±320 mV), and DC voltage up to -2 V does not cause latch-up or damage. |
| 3 | VIN- | power_in | Negative analog input with recommended input range ±200 mV (full-scale ±320 mV), normally connected to GND1. |
| 4 | GND1 | power_in | Supply ground for the signal input side, which is the reference for VDD1 and the analog inputs. |
| 5 | GND2 | power_in | Supply ground for the data/clock output (digital) side, which is the reference for VDD2. |
| 6 | MDAT | output | Modulator data output, a 1-bit data stream at 10 MHz with digital output limits of -0.5 V to VDD2 + 0.5 V. |
| 7 | MCLK | output | Modulator clock output, 9 MHz to 11 MHz (10 MHz typical) with 40% to 60% duty cycle at 15 pF load, with digital output limits of -0.5 V to VDD2 + 0.5 V. |
| 8 | VDD2 | power_in | Supply voltage for the data output (digital) side, relative to GND2, recommended 3 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SO-8 |
| Category | Optoisolators |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `ACPL-C797-500E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `acpl-c797-500e-etched.step` / `acpl-c797-500e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acpl-c797-500e.step` / `acpl-c797-500e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Broadcom AVAGO datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588917230528159744) (18 pp, sha256 `4a397abbec5ea019`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/acpl-c797-500e-datasheet.pdf)