component
ACPL-C790-500E
Public Made by Adomby adom
Broadcom AVAGO Operational Amplifier, SO-8-6.8mm. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
2 files changed
+267−1
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/acpl-c790-500e-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+265@@ -0,0 +1,265 @@+{+ "schema": "adom.pads/1",+ "slug": "acpl-c790-500e",+ "footprint": "SOIC-8_3.9x4.9mm_P1.27mm",+ "generated_from": {+ "footprint": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.475,+ -1.905+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4"+ },+ "pad_count": 8,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "VDD1",+ "type": "power_in",+ "description": "Input-side supply voltage, 4.5 V to 5.5 V referenced to GND1. Requires a 0.1 µF bypass capacitor between pins 1 and 4. Typical input-side supply current IDD1 = 11 mA (18.5 mA max).",+ "is_pin1": true,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "VIN+",+ "type": "input",+ "description": "Positive analog input. Nominal input range ±200 mV (full-scale ±300 mV, functional ±2 V) relative to VIN-. Input bias current typ. -0.1 µA; single-ended input impedance 27 kΩ.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "VIN-",+ "type": "input",+ "description": "Negative analog input, normally connected to GND1 for single-ended sensing. Same ±200 mV nominal range and 27 kΩ single-ended input impedance as VIN+.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "GND1",+ "type": "power_in",+ "description": "Input-side ground reference for VDD1, VIN+ and VIN-.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "GND2",+ "type": "power_in",+ "description": "Output-side ground reference for VDD2, VOUT+ and VOUT-. Galvanically isolated from GND1 by the optical barrier (VIORM = 1414 Vpeak, 5000 Vrms/1 min).",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "6",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "6",+ "name": "VOUT-",+ "type": "output",+ "description": "Negative differential analog output. Output common-mode voltage 1.23 V, output voltage range 0 V to 2.5 V, output resistance ~21 Ω, short-circuit current ~11 mA.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "7",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "7",+ "name": "VOUT+",+ "type": "output",+ "description": "Positive differential analog output. Output common-mode voltage 1.23 V, output voltage range 0 V to 2.5 V, output resistance ~21 Ω, short-circuit current ~11 mA.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "8",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "8",+ "name": "VDD2",+ "type": "power_in",+ "description": "Output-side supply voltage, 3 V to 5.5 V referenced to GND2. Requires a 0.1 µF bypass capacitor between pins 5 and 8. Typical IDD2 = 7 mA at 5 V (6.8 mA at 3.3 V).",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}