ACPL-C784-500E

{
  "slug": "acpl-c784-500e",
  "version": "0.1.0",
  "type": "component",
  "description": "Broadcom AVAGO Logic Output Optoisolators, SO-8-6.8mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "optoisolators",
    "acpl-c784-500e",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "acpl-c784-500e.kicad_sym",
    "acpl-c784-500e.kicad_mod",
    "acpl-c784-500e.glb",
    "acpl-c784-500e.step",
    "acpl-c784-500e.lbr",
    "docs/hero.png",
    "docs/acpl-c784-500e-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "acpl-c784-500e-hero.glb",
    "acpl-c784-500e-hero.overlay.json",
    "acpl-c784-500e-etched.glb"
  ],
  "component": {
    "mpn": "ACPL-C784-500E",
    "manufacturer": "Broadcom AVAGO",
    "package": "SO-8-6.8mm",
    "pin_count": 8,
    "category": "Optoisolators",
    "subcategory": "Logic Output Optoisolators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588917489879564289",
    "parts": {
      "symbol": "acpl-c784-500e.kicad_sym",
      "footprint": "acpl-c784-500e.kicad_mod",
      "model_3d": "acpl-c784-500e-hero.glb",
      "model_3d_plain": "acpl-c784-500e-etched.glb",
      "model_3d_step": "acpl-c784-500e-etched.step",
      "model_3d_step_plain": "acpl-c784-500e.step",
      "lbr": "acpl-c784-500e.lbr"
    },
    "distributor_links": {
      "lcsc": "C691939",
      "digikey": "516-3728-2-ND",
      "mouser": "630-ACPL-C784-500E"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T04:02:00Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "516-3728-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "630-ACPL-C784-500E",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD1",
        "type": "power_in",
        "description": "Input-side supply voltage, 4.5 V to 5.5 V relative to GND1, with a 0.1 µF bypass capacitor required between pins 1 and 4."
      },
      {
        "number": "2",
        "name": "VIN+",
        "type": "power_in",
        "description": "Positive input, with ±200 mV recommended for linear and accurate operation."
      },
      {
        "number": "3",
        "name": "VIN–",
        "type": "power_in",
        "description": "Negative input, normally connected to GND1 (pin 4)."
      },
      {
        "number": "4",
        "name": "GND1",
        "type": "power_in",
        "description": "Input-side ground, the reference for VDD1 and VIN-."
      },
      {
        "number": "5",
        "name": "GND2",
        "type": "power_in",
        "description": "Output-side ground, the reference for VDD2 and the outputs, with a 0.1 µF bypass capacitor required between pins 5 and 8."
      },
      {
        "number": "6",
        "name": "VOUT–",
        "type": "output",
        "description": "Negative differential output, which together with VOUT+ carries the amplified input signal."
      },
      {
        "number": "7",
        "name": "VOUT+",
        "type": "output",
        "description": "Positive differential output, which together with VOUT- carries the amplified input signal."
      },
      {
        "number": "8",
        "name": "VDD2",
        "type": "power_in",
        "description": "Output-side supply voltage, 4.5 V to 5.5 V relative to GND2, with a 0.1 µF bypass capacitor required between pins 5 and 8."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The ordering table on page 2 lists the -500E option (RoHS compliant, surface mount, tape and reel, 1; Pin types were assigned from the KiCad ERC classes. The datasheet does not state pin types, so VOUT+"
        ],
        "pages_sent": 17,
        "cost_usd": 0.0819,
        "at": "2026-10-18T04:00:14"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588917489879564289",
        "pages": 17,
        "sha256": "e22d3e7f4b47b07e",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
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        "file": "acpl-c784-500e.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "acpl-c784-500e-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "4d2d02e3bd490687915b516f1789c02f25cbebe347b993ef68b5cc6847e45ec6",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}