component
ACPL-355JC-500E
Public Made by Adomby adom
Broadcom/AVAGO Gate Drive Optocoupler, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ACPL-355JC-500E
Broadcom/AVAGO · Gate Drive Optocoupler · SO-16
ACPL-355JC-500E from Broadcom/AVAGO, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSS1 | power_in | Input ground. |
| 2 | UVLO | output | VDD2 under voltage lockout feedback output. |
| 3 | FAULT | output | Overcurrent fault feedback output, changes from logic high to low when the OC pin exceeds the 9V internal reference while the IGBT/MOSFET is on. |
| 4 | VDD1 | power_in | Input power supply. |
| 5 | NC | unconnected | No connection. |
| 6 | ANODE | input | Input LED anode (pins 6 and 7 are both anode). |
| 7 | ANODE | input | Input LED anode (pins 6 and 7 are both anode). |
| 8 | CATHODE | input | Input LED cathode. |
| 9 | VS | power_in | Common (IGBT emitter or MOSFET source) output supply voltage. |
| 10 | VOUTN | output | Driver output to turn off the IGBT or MOSFET gate. |
| 11 | VOUTP/CLAMP | output | Driver output to turn on the IGBT or MOSFET gate, also used as Miller clamp. |
| 12 | VDD2 | power_in | Positive output power supply, 15V to 30V operating range. |
| 13 | SS | passive | Soft shutdown pin for configurable soft shutdown on overcurrent. |
| 14 | OC | input | Overcurrent input; when its voltage exceeds the internal 9V reference while the IGBT/MOSFET is on, FAULT changes from logic high to low. |
| 15 | NC | unconnected | No connection (labelled (LED2)NC). |
| 16 | VSS2 | power_in | Negative output power supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom/AVAGO |
| Package | SO-16 |
| Category | Optoisolators |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TS | -55 | 125 | °C | 6 | ||
| Operating Temperature (abs max) | TA | -40 | 110 | °C | 6 | ||
| Output IC Junction Temperature | TJ | 125 | °C | 6 | |||
| Average Input Current | IF(AVG) | 25 | mA | Derate linearly above 70°C at 0.3 mA/°C | 6 | ||
| Peak Transient Input Current | IF(TRAN) | 1 | A | < 1-μs pulse width, 300pps | 6 | ||
| Reverse Input Voltage | VR | 5 | V | 6 | |||
| Peak Output Current | IO(PEAK) | 10 | A | Max pulse width = 1 μs, max duty cycle = 1% | 6 | ||
| Positive Input Supply Voltage | VDD1 | 0 | 7 | V | 6 | ||
| FAULT Output Current | IFAULT | 10 | mA | 6 | |||
| Total Output Supply Voltage | VDD2, VSS2 | -0.5 | 35 | V | 6 | ||
| Negative Output Supply Voltage | VS, VSS2 | -0.5 | 17 | V | 6 | ||
| Input Current Rise/Fall Time | tr(IN)/tf(IN) | 500 | ns | 6 | |||
| Peak Clamp Sinking Current | ICLAMP | 4 | A | 6 | |||
| Output IC Power Dissipation | PO | 600 | mW | Derate linearly above 95°C at 20 mW/°C | 6 | ||
| Input LED Power Dissipation | PI | 110 | mW | Derate linearly above 95°C at 3.7 mW/°C | 6 | ||
| Operating Temperature | TA | -40 | 110 | °C | 6 | ||
| Positive Input Supply Voltage | VDD1 | 4.5 | 5.5 | V | 6 | ||
| Total Output Supply Voltage | VDD2, VSS2 | 15 | 30 | V | 6 | ||
| Negative Output Supply Voltage | VS, VSS2 | 0 | 15 | V | 6 | ||
| Input Current (ON) | IF(ON) | 7 | 11 | mA | 6 | ||
| Input Voltage (OFF) | VF(OFF) | -3.6 | 0.5 | V | 6 | ||
| VOUTP High Level Peak Output Current | IOH | -7.5 | -13 | A | VDD2, VOUTP = 15V | 7 | |
| VOUTN Low Level Peak Output Current | IOL | 7.5 | 14 | A | VOUTN, VSS2 = 15V | 7 | |
| VOUTP Output PMOS RDS(ON) | ROUTP | 0.4 | 0.7 | 1.5 | Ω | IOP = -7.5A, IF = 8 mA | 7 |
| VOUTN Output NMOS RDS(ON) | ROUTN | 0.3 | 0.4 | 1.2 | Ω | ION = 7.5A, VF = 0V | 7 |
| VOUTP Output Voltage | VOH | -0.6 | -0.15 | V | IOP = -100 mA, IF = 8 mA; printed as VDD2, 0.60 min, VDD2, 0.15 typ | 7 | |
| VOUTN Output Voltage | VOL | 0.04 | 0.6 | V | ION = 100 mA, VF = 0V; printed as VSS2 + value | 7 | |
| Clamp Threshold Voltage | VTH_CLAMP | 2 | 2.2 | V | printed as VSS2 + value | 7 | |
| Clamp Low Level Sinking Current | ICLAMP | 1.7 | 2.75 | A | VCLAMP = VSS2 + 2.5V | 7 | |
| Clamp Low Level Peak Sinking Current | ICLAMPPK | 2.5 | 4.6 | A | VCLAMP = VSS2 + 10V | 7 | |
| Clamp Output Transistor RDS(ON) | RDS,CLAMP | 1.1 | 2 | Ω | ICLAMP = 2.5A | 7 | |
| SS Pull Down Current | IOSS | 0.5 | 1 | A | SS, VSS2 < 15V, IF = 8 mA, OC = Open | 7 | |
| High Level Output Supply Current (VDD2) | IDD2H | 6.5 | 8 | mA | IF = 8 mA, No Load | 7 | |
| Low Level Output Supply Current (VDD2) | IDD2L | 5.4 | 7 | mA | VF = 0V, No Load | 7 | |
| High Level Output Supply Current (VSS2) | ISS2H | -2.2 | -1.7 | mA | IF = 8 mA, No Load | 7 | |
| Low Level Output Supply Current (VSS2) | ISS2L | -1 | -0.7 | mA | VF = 0V, No Load | 7 | |
| Input Threshold Current Low to High | IFLH | 0.2 | 2.5 | 6.5 | mA | 7 | |
| Input Threshold Voltage High to Low | VFHL | 0.8 | V | 7 | |||
| Input Forward Voltage | VF | 1.2 | 1.4 | 1.95 | V | IF = 8 mA | 7 |
| Input Reverse Breakdown Voltage | BVR | 5 | V | IR = 100 μA | 7 | ||
| UVLO Threshold positive-going | VUVLO+ | 12.2 | 13.2 | 13.8 | V | IF = 8 mA, VOUTP, VE > 5V | 8 |
| UVLO Threshold negative-going | VUVLO- | 11.2 | 12.1 | 12.7 | V | IF = 8 mA, VOUTP, VE < 5V | 8 |
| UVLO Hysteresis | VUVLO+, VUVLO- | 0.5 | 1 | V | 8 | ||
| OC Sensing Voltage Threshold | VOC | 8.5 | 9.2 | 9.8 | V | VDD2, VS > VUVLO+ | 8 |
| Blanking Capacitor Charging Current | ICHG | 0.95 | 1 | 1.05 | mA | VOC = 2V | 8 |
| OC Low Voltage when Blanking Capacitor Discharge | VDSCHG | 1.4 | 2.3 | V | IDSCHG = 50 mA | 8 | |
| Input Supply Current (VDD1) | IDD1 | 1.6 | 2.5 | mA | 8 | ||
| FAULT Logic Low Output Current | IFAULTL | 4 | 8.5 | mA | VFAULT = 0.4 V, VDD1 = 5V | 8 | |
| FAULT Logic High Output Current | IFAULTH | 20 | μA | VFAULT = VDD1 = 5V | 8 | ||
| UVLO Logic Low Output Current | IUVLOL | 4 | 8.5 | mA | VUVLO = 0.4 V, VDD1 = 5V | 8 | |
| UVLO Logic High Output Current | IUVLOH | 20 | μA | VUVLO = VDD1 = 5V | 8 | ||
| Propagation Delay Time to High | tPLH | 40 | 90 | 140 | ns | RGP = 3Ω, RGN = 3Ω, CG = 2.2 nF, f = 20 kHz, Duty Cycle = 50%, IF = 8 mA | 9 |
| Propagation Delay Time to Low | tPHL | 40 | 100 | 140 | ns | RGP = 3Ω, RGN = 3Ω, CG = 2.2 nF, f = 20 kHz, Duty Cycle = 50%, IF = 8 mA | 9 |
| Pulse Width Distortion | PWD | -50 | 10 | 50 | ns | 9 | |
| Propagation Delay Difference Between Any Two Parts | PDD | -70 | 70 | ns | 9 | ||
| Propagation Delay Skew | tPSK | 60 | ns | 9 | |||
| OC Blanking Time | tOC(BLANKING) | 0.6 | 1 | μs | f = 2.5kHz, Duty Cycle = 50%, IF = 8 mA, RSS = 15Ω, CF = 330 pF, RF = 10 kΩ | 9 | |
| OC Detection to 90% VGATE Delay | tOC(90%) | 0.05 | 0.13 | 0.3 | μs | 9 | |
| OC Detection to VGATE = 2V Delay | tOC(2V) | 0.1 | 0.2 | 0.5 | μs | 9 | |
| OC Detection to SS Pull Low Delay | tSS(LOW) | 0.35 | 0.8 | μs | 9 | ||
| OC Detection to Low Level FAULT Signal Delay | tOC(FAULT) | 1.7 | 5 | μs | 9 | ||
| Output Mute Time due to Overcurrent | tOC(MUTE) | 0.13 | 0.2 | 0.4 | ms | 9 | |
| Time Input Kept Low Before Fault Reset to High | tOC(RESET) | 0.13 | 0.2 | 0.4 | ms | CF = 330 pF, RF = 10 kΩ | 9 |
| VDD2 to UVLO High Delay | tPLH_UVLO | 17 | 25 | μs | CU = 330 pF, RU = 10 kΩ | 9 | |
| VDD2 to UVLO Low Delay | tPHL_UVLO | 14 | 30 | μs | CU = 330 pF, RU = 10 kΩ | 9 | |
| Output High Level Common Mode Transient Immunity | /CMH/ | 100 | kV/μs | TA = 25°C, VCM = 1500V, VDD1 = 5V, CF = 330 pF, RF = 10 kΩ, IF = 8 mA | 9 | ||
| Output Low Level Common Mode Transient Immunity | /CML/ | 100 | kV/μs | TA = 25°C, VCM = 1500V, VDD1 = 5V, CF = 330 pF, RF = 10 kΩ, VF = 0V | 9 | ||
| Input-Output Momentary Withstand Voltage | VISO | 5000 | VRMS | RH < 50%, t = 1 minute, TA = 25°C | 11 |
CAD (KiCad official)
- Symbol:
ACPL-355JC-500E - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
acpl-355jc-500e-etched.step/acpl-355jc-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acpl-355jc-500e.step/acpl-355jc-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom/AVAGO datasheet (29 pp, sha256
3ef4e90991ff1084, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ACPL-355JC-500E
**Broadcom/AVAGO** · Gate Drive Optocoupler · SO-16
ACPL-355JC-500E from Broadcom/AVAGO, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSS1 | power_in | Input ground. |
| 2 | UVLO | output | VDD2 under voltage lockout feedback output. |
| 3 | FAULT | output | Overcurrent fault feedback output, changes from logic high to low when the OC pin exceeds the 9V internal reference while the IGBT/MOSFET is on. |
| 4 | VDD1 | power_in | Input power supply. |
| 5 | NC | unconnected | No connection. |
| 6 | ANODE | input | Input LED anode (pins 6 and 7 are both anode). |
| 7 | ANODE | input | Input LED anode (pins 6 and 7 are both anode). |
| 8 | CATHODE | input | Input LED cathode. |
| 9 | VS | power_in | Common (IGBT emitter or MOSFET source) output supply voltage. |
| 10 | VOUTN | output | Driver output to turn off the IGBT or MOSFET gate. |
| 11 | VOUTP/CLAMP | output | Driver output to turn on the IGBT or MOSFET gate, also used as Miller clamp. |
| 12 | VDD2 | power_in | Positive output power supply, 15V to 30V operating range. |
| 13 | SS | passive | Soft shutdown pin for configurable soft shutdown on overcurrent. |
| 14 | OC | input | Overcurrent input; when its voltage exceeds the internal 9V reference while the IGBT/MOSFET is on, FAULT changes from logic high to low. |
| 15 | NC | unconnected | No connection (labelled (LED2)NC). |
| 16 | VSS2 | power_in | Negative output power supply. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom/AVAGO |
| Package | SO-16 |
| Category | Optoisolators |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TS | -55 | | 125 | °C | | 6 |
| Operating Temperature (abs max) | TA | -40 | | 110 | °C | | 6 |
| Output IC Junction Temperature | TJ | | | 125 | °C | | 6 |
| Average Input Current | IF(AVG) | | | 25 | mA | Derate linearly above 70°C at 0.3 mA/°C | 6 |
| Peak Transient Input Current | IF(TRAN) | | | 1 | A | < 1-μs pulse width, 300pps | 6 |
| Reverse Input Voltage | VR | | | 5 | V | | 6 |
| Peak Output Current | IO(PEAK) | | | 10 | A | Max pulse width = 1 μs, max duty cycle = 1% | 6 |
| Positive Input Supply Voltage | VDD1 | 0 | | 7 | V | | 6 |
| FAULT Output Current | IFAULT | | | 10 | mA | | 6 |
| Total Output Supply Voltage | VDD2, VSS2 | -0.5 | | 35 | V | | 6 |
| Negative Output Supply Voltage | VS, VSS2 | -0.5 | | 17 | V | | 6 |
| Input Current Rise/Fall Time | tr(IN)/tf(IN) | | | 500 | ns | | 6 |
| Peak Clamp Sinking Current | ICLAMP | | | 4 | A | | 6 |
| Output IC Power Dissipation | PO | | | 600 | mW | Derate linearly above 95°C at 20 mW/°C | 6 |
| Input LED Power Dissipation | PI | | | 110 | mW | Derate linearly above 95°C at 3.7 mW/°C | 6 |
| Operating Temperature | TA | -40 | | 110 | °C | | 6 |
| Positive Input Supply Voltage | VDD1 | 4.5 | | 5.5 | V | | 6 |
| Total Output Supply Voltage | VDD2, VSS2 | 15 | | 30 | V | | 6 |
| Negative Output Supply Voltage | VS, VSS2 | 0 | | 15 | V | | 6 |
| Input Current (ON) | IF(ON) | 7 | | 11 | mA | | 6 |
| Input Voltage (OFF) | VF(OFF) | -3.6 | | 0.5 | V | | 6 |
| VOUTP High Level Peak Output Current | IOH | -7.5 | -13 | | A | VDD2, VOUTP = 15V | 7 |
| VOUTN Low Level Peak Output Current | IOL | 7.5 | 14 | | A | VOUTN, VSS2 = 15V | 7 |
| VOUTP Output PMOS RDS(ON) | ROUTP | 0.4 | 0.7 | 1.5 | Ω | IOP = -7.5A, IF = 8 mA | 7 |
| VOUTN Output NMOS RDS(ON) | ROUTN | 0.3 | 0.4 | 1.2 | Ω | ION = 7.5A, VF = 0V | 7 |
| VOUTP Output Voltage | VOH | -0.6 | -0.15 | | V | IOP = -100 mA, IF = 8 mA; printed as VDD2, 0.60 min, VDD2, 0.15 typ | 7 |
| VOUTN Output Voltage | VOL | | 0.04 | 0.6 | V | ION = 100 mA, VF = 0V; printed as VSS2 + value | 7 |
| Clamp Threshold Voltage | VTH_CLAMP | | 2 | 2.2 | V | printed as VSS2 + value | 7 |
| Clamp Low Level Sinking Current | ICLAMP | 1.7 | 2.75 | | A | VCLAMP = VSS2 + 2.5V | 7 |
| Clamp Low Level Peak Sinking Current | ICLAMPPK | 2.5 | 4.6 | | A | VCLAMP = VSS2 + 10V | 7 |
| Clamp Output Transistor RDS(ON) | RDS,CLAMP | | 1.1 | 2 | Ω | ICLAMP = 2.5A | 7 |
| SS Pull Down Current | IOSS | 0.5 | 1 | | A | SS, VSS2 < 15V, IF = 8 mA, OC = Open | 7 |
| High Level Output Supply Current (VDD2) | IDD2H | | 6.5 | 8 | mA | IF = 8 mA, No Load | 7 |
| Low Level Output Supply Current (VDD2) | IDD2L | | 5.4 | 7 | mA | VF = 0V, No Load | 7 |
| High Level Output Supply Current (VSS2) | ISS2H | -2.2 | -1.7 | | mA | IF = 8 mA, No Load | 7 |
| Low Level Output Supply Current (VSS2) | ISS2L | -1 | -0.7 | | mA | VF = 0V, No Load | 7 |
| Input Threshold Current Low to High | IFLH | 0.2 | 2.5 | 6.5 | mA | | 7 |
| Input Threshold Voltage High to Low | VFHL | 0.8 | | | V | | 7 |
| Input Forward Voltage | VF | 1.2 | 1.4 | 1.95 | V | IF = 8 mA | 7 |
| Input Reverse Breakdown Voltage | BVR | 5 | | | V | IR = 100 μA | 7 |
| UVLO Threshold positive-going | VUVLO+ | 12.2 | 13.2 | 13.8 | V | IF = 8 mA, VOUTP, VE > 5V | 8 |
| UVLO Threshold negative-going | VUVLO- | 11.2 | 12.1 | 12.7 | V | IF = 8 mA, VOUTP, VE < 5V | 8 |
| UVLO Hysteresis | VUVLO+, VUVLO- | 0.5 | 1 | | V | | 8 |
| OC Sensing Voltage Threshold | VOC | 8.5 | 9.2 | 9.8 | V | VDD2, VS > VUVLO+ | 8 |
| Blanking Capacitor Charging Current | ICHG | 0.95 | 1 | 1.05 | mA | VOC = 2V | 8 |
| OC Low Voltage when Blanking Capacitor Discharge | VDSCHG | | 1.4 | 2.3 | V | IDSCHG = 50 mA | 8 |
| Input Supply Current (VDD1) | IDD1 | | 1.6 | 2.5 | mA | | 8 |
| FAULT Logic Low Output Current | IFAULTL | 4 | 8.5 | | mA | VFAULT = 0.4 V, VDD1 = 5V | 8 |
| FAULT Logic High Output Current | IFAULTH | | | 20 | μA | VFAULT = VDD1 = 5V | 8 |
| UVLO Logic Low Output Current | IUVLOL | 4 | 8.5 | | mA | VUVLO = 0.4 V, VDD1 = 5V | 8 |
| UVLO Logic High Output Current | IUVLOH | | | 20 | μA | VUVLO = VDD1 = 5V | 8 |
| Propagation Delay Time to High | tPLH | 40 | 90 | 140 | ns | RGP = 3Ω, RGN = 3Ω, CG = 2.2 nF, f = 20 kHz, Duty Cycle = 50%, IF = 8 mA | 9 |
| Propagation Delay Time to Low | tPHL | 40 | 100 | 140 | ns | RGP = 3Ω, RGN = 3Ω, CG = 2.2 nF, f = 20 kHz, Duty Cycle = 50%, IF = 8 mA | 9 |
| Pulse Width Distortion | PWD | -50 | 10 | 50 | ns | | 9 |
| Propagation Delay Difference Between Any Two Parts | PDD | -70 | | 70 | ns | | 9 |
| Propagation Delay Skew | tPSK | | | 60 | ns | | 9 |
| OC Blanking Time | tOC(BLANKING) | | 0.6 | 1 | μs | f = 2.5kHz, Duty Cycle = 50%, IF = 8 mA, RSS = 15Ω, CF = 330 pF, RF = 10 kΩ | 9 |
| OC Detection to 90% VGATE Delay | tOC(90%) | 0.05 | 0.13 | 0.3 | μs | | 9 |
| OC Detection to VGATE = 2V Delay | tOC(2V) | 0.1 | 0.2 | 0.5 | μs | | 9 |
| OC Detection to SS Pull Low Delay | tSS(LOW) | | 0.35 | 0.8 | μs | | 9 |
| OC Detection to Low Level FAULT Signal Delay | tOC(FAULT) | | 1.7 | 5 | μs | | 9 |
| Output Mute Time due to Overcurrent | tOC(MUTE) | 0.13 | 0.2 | 0.4 | ms | | 9 |
| Time Input Kept Low Before Fault Reset to High | tOC(RESET) | 0.13 | 0.2 | 0.4 | ms | CF = 330 pF, RF = 10 kΩ | 9 |
| VDD2 to UVLO High Delay | tPLH_UVLO | | 17 | 25 | μs | CU = 330 pF, RU = 10 kΩ | 9 |
| VDD2 to UVLO Low Delay | tPHL_UVLO | | 14 | 30 | μs | CU = 330 pF, RU = 10 kΩ | 9 |
| Output High Level Common Mode Transient Immunity | /CMH/ | 100 | | | kV/μs | TA = 25°C, VCM = 1500V, VDD1 = 5V, CF = 330 pF, RF = 10 kΩ, IF = 8 mA | 9 |
| Output Low Level Common Mode Transient Immunity | /CML/ | 100 | | | kV/μs | TA = 25°C, VCM = 1500V, VDD1 = 5V, CF = 330 pF, RF = 10 kΩ, VF = 0V | 9 |
| Input-Output Momentary Withstand Voltage | VISO | 5000 | | | VRMS | RH < 50%, t = 1 minute, TA = 25°C | 11 |
## CAD (KiCad official)
- Symbol: `ACPL-355JC-500E`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files: `acpl-355jc-500e-etched.step` / `acpl-355jc-500e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acpl-355jc-500e.step` / `acpl-355jc-500e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Broadcom/AVAGO datasheet](docs/acpl-355jc-500e-datasheet.pdf) (29 pp, sha256 `3ef4e90991ff1084`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/acpl-355jc-500e-datasheet.pdf)