# ACPL-074L-000E

**Broadcom/AVAGO** · Logic Output Optocoupler · SOP-8

ACPL-074L-000E from Broadcom/AVAGO, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ANODE1 | input | Anode of the channel 1 input LED; the datasheet recommends a series limiting resistor of 210 Ω at 5 V input or 80 Ω at 3.3 V input. |
| 2 | CATHODE1 | passive | Cathode of the channel 1 input LED, which is driven with an average forward input current of 14 mA in the test conditions. |
| 3 | CATHODE2 | passive | Cathode of the channel 2 input LED, which is driven with an average forward input current of 14 mA in the test conditions. |
| 4 | ANODE2 | input | Anode of the channel 2 input LED; the datasheet recommends a series limiting resistor of 210 Ω at 5 V input or 80 Ω at 3.3 V input. |
| 5 | GND | power_in | Ground reference for the output detector circuitry, to be decoupled to VDD with a 0.1 µF bypass capacitor placed as close as possible to the pins. |
| 6 | VO2 | output | Channel 2 CMOS logic output, which is HIGH when the channel 2 LED is off and LOW when it is on. |
| 7 | VO1 | output | Channel 1 CMOS logic output, which is HIGH when the channel 1 LED is off and LOW when it is on. |
| 8 | VDD | power_in | Detector supply voltage, specified at 3.0 V to 3.6 V or 4.5 V to 5.5 V, with a minimum of 3.0 V required before the output-connected component is powered. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Broadcom/AVAGO |
| Package | SOP-8 |
| Category | Optocoupler |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TS | -55 |  | 125 | °C |  | 6 |
| Ambient Operating Temperature | TA | -40 |  | 105 | °C |  | 6 |
| Supply Voltages | VDD | 0 |  | 6 | Volts |  | 6 |
| Output Voltage | VO | -0.5 |  |  | Volts |  | 6 |
| Average Forward Input Current | IF |  |  | 20 | mA |  | 6 |
| Average Output Current | Io |  |  | 10 | mA |  | 6 |
| Input Power Dissipation | PI |  |  | 35 | mW |  | 6 |
| Output Power Dissipation | PO |  |  | 100 | mW |  | 6 |
| Ambient Operating Temperature | TA | -40 |  | 105 | °C |  | 6 |
| Supply Voltages | VDD | 4.5 |  | 5.5 | V |  | 6 |
| Supply Voltages | VDD | 3 |  | 3.6 | V |  | 6 |
| Input Current (ON) | IF | 12 |  | 18 | mA |  | 6 |
| Supply Voltage Slew Rate | SR | 0.5 |  | 500 | V/ms |  | 6 |
| Input Forward Voltage | VF | 1.3 | 1.5 | 1.8 | V | IF = 14 mA | 6 |
| Input Reverse Breakdown Voltage | BVR | 5 |  |  | V | IR = 10 µA | 6 |
| Logic Low Output Voltage (3.3V) | VOL |  | 0.35 | 0.8 | V | IF = 14 mA, IO = 4 mA, VDD = 3.3V | 6 |
| Logic Low Output Voltage (5V) | VOL |  | 0.2 | 0.8 | V | IF = 14 mA, IO = 4 mA, VDD = 5V | 6 |
| Input Threshold Current | ITH |  | 4.5 | 8.8 | mA | IOL = 20 µA | 6 |
| Logic Low Output Supply Current (ACPL-074L) | IDDL |  | 8.3 | 12 | mA | IF = 14 mA | 6 |
| Logic High Output Supply Current (ACPL-074L) | IDDH |  | 7.6 | 12 | mA | IF = 0 | 6 |
| Propagation Delay Time to Logic Low Output (3.3V) | tPHL |  | 29 | 40 | ns | IF = 14 mA, CL = 15 pF, VDD = 3.3V, CMOS Signal Levels | 7 |
| Propagation Delay Time to Logic Low Output (5V) | tPHL |  |  | 50 | ns | IF = 14 mA, CL = 15 pF, VDD = 5V, CMOS Signal Levels | 7 |
| Propagation Delay Time to Logic High Output (3.3V) | tPLH |  | 22 | 40 | ns | IF = 14 mA, CL = 15 pF, VDD = 3.3V, CMOS Signal Levels | 7 |
| Propagation Delay Time to Logic High Output (5V) | tPLH |  |  | 50 | ns | IF = 14 mA, CL = 15 pF, VDD = 5V, CMOS Signal Levels | 7 |
| Pulse Width | tPW | 66.7 |  |  | ns |  | 7 |
| Pulse Width Distortion (3.3V) | /PWD/ | 0 | 7 | 25 | ns | IF = 14 mA, CL = 15 pF, VDD = 3.3V, CMOS Signal Levels | 7 |
| Pulse Width Distortion (5V) | /PWD/ |  |  | 30 | ns | IF = 14 mA, CL = 15 pF, VDD = 5V, CMOS Signal Levels | 7 |
| Propagation Delay Skew | tPSK |  |  | 30 | ns | IF = 14 mA, CL = 15 pF, CMOS Signal Levels | 7 |
| Output Rise Time (10% - 90%) | tR |  | 20 |  | ns | IF = 14 mA, CL = 15 pF, CMOS Signal Levels | 7 |
| Output Fall Time (90% - 10%) | tF |  | 25 |  | ns | IF = 14 mA, CL = 15 pF, CMOS Signal Levels | 7 |
| Common Mode Transient Immunity at Logic High Output | /CMH/ | 10 | 15 |  | kV/µs | VCM = 1000 V, TA = 25°C, IF = 0 mA | 7 |
| Common Mode Transient Immunity at Logic Low Output | /CML/ | 10 | 15 |  | kV/µs | VCM = 1000 V, TA = 25°C, IF = 14 mA | 7 |
| Input-Output Insulation | II-O |  |  | 1 | µA | 45% RH, t = 5s, VI-O = 3 kV DC, TA = 25°C | 7 |
| Input-Output Momentary Withstand Voltage | VISO | 3750 |  |  | Vrms | RH 50%, t = 1 min., TA = 25°C | 7 |
| Input-Output Resistance | R I-O |  | 1012 |  | Ω | VI-O = 500 V dc | 7 |
| Input-Output Capacitance | C I-O |  | 0.6 |  | pF | f = 1 MHz, TA = 25°C | 7 |

## CAD (KiCad official)

- Symbol: `ACPL-074L-000E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `acpl-074l-000e-etched.step` / `acpl-074l-000e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `acpl-074l-000e.step` / `acpl-074l-000e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Broadcom/AVAGO datasheet](docs/acpl-074l-000e-datasheet.pdf) (11 pp, sha256 `72cec7c12d0199e1`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/acpl-074l-000e-datasheet.pdf)