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AC78013MDQA

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AutoChips Microcontrollers (MCU/MPU/SOC), QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AC78013MDQA

AutoChips · Microcontrollers (MCU/MPU/SOC) · QFN-32(5x5)

AC78013MDQA from AutoChips, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB0 bidirectional Port B bit 0 GPIO, which powers up as GPIO and can alternatively be set to CAN_TX, PWM0_CH7 or SPI1_MISO via PMUX1[20:18].
2 PB1 bidirectional Port B bit 1 GPIO, which powers up as GPIO and can alternatively be set to CAN_RX, PWM0_CH6 or SPI1_NSS via PMUX1[23:21].
3 VDD1 power_in Digital supply pin 1; operating voltage is 2.7 to 5.5 V and absolute maximum VDD is -0.3 to 6 V, decoupled to VSS1 with a 0.1 µF X7R capacitor placed close to the pins.
4 VSS1 power_in Ground pin 1 for the digital supply, decoupled against VDD1 with a low-ESR 0.1 µF X7R capacitor placed as close as possible to the pins.
5 PA12 output Default function OSC_OUT1 is the output of the external crystal oscillator (4 to 30 MHz); load capacitors must include about 10 pF of pin and board capacitance.
6 PA15 input Default function OSC_IN1 is the input of the external crystal oscillator (4 to 30 MHz); load capacitors must include about 10 pF of pin and board capacitance.
7 PA0 bidirectional Port A bit 0 GPIO, which powers up as GPIO and can alternatively be set to PWM0_CH1, UART0_RTS or I2C0_SCL via PMUX0[2:0].
8 PA1 bidirectional Port A bit 1 GPIO, which powers up as GPIO and can alternatively be set to PWM0_CH0, UART0_CTS or I2C0_SDA via PMUX0[5:3].
9 PB3 bidirectional Port B bit 3 GPIO, which powers up as GPIO and can alternatively be set to PWM0_CH6, PWM1_CH7 or SPI0_MOSI via PMUX1[29:27].
10 PA2 bidirectional Port A bit 2 GPIO, which powers up as GPIO and can alternatively be set to PWM0_CH5, ADC_IN8 or SPI0_MISO via PMUX0[8:6].
11 PA3 bidirectional Port A bit 3 GPIO, which powers up as GPIO and can alternatively be set to PWM0_CH4, ADC_IN7 or SPI0_SCK via PMUX0[11:9].
12 PA4 bidirectional Port A bit 4 GPIO, which powers up as GPIO and can alternatively be set to PWM0_CH3, ADC_IN6/ACMP_IN6 or UART1_TX via PMUX0[14:12].
13 PA5 bidirectional Port A bit 5 GPIO, which powers up as GPIO and can alternatively be set to PWM0_CH2, ADC_IN5/ACMP_IN5 or UART1_RX via PMUX0[17:15].
14 PA6 bidirectional Port A bit 6 GPIO, which powers up as GPIO and can alternatively be set to the BOOT1 function via PMUX0[20:18].
15 PB4 bidirectional Port B bit 4 GPIO, which powers up as GPIO and can alternatively be set to PWM1_CH1, ADC_IN8 or SPI0_MISO via PMUX2[2:0].
16 PB5 bidirectional Port B bit 5 GPIO, which powers up as GPIO and can alternatively be set to PWM1_CH0, ADC_IN7 or SPI0_SCK via PMUX2[5:3].
17 PA7 bidirectional Port A bit 7 GPIO, which powers up as GPIO and can alternatively be set to UART0_TX, ADC_IN4/ACMP_IN4 or SPI0_MOSI via PMUX0[23:21].
18 PA8 bidirectional Port A bit 8 GPIO, which powers up as GPIO and can alternatively be set to UART0_RX, ADC_IN3/ACMP_IN3 or SPI0_NSS via PMUX0[26:24].
19 PA9 bidirectional Port A bit 9 GPIO, which powers up as GPIO and can alternatively be set to PWM0_FLT0, ADC_IN2/ACMP_IN2 or RTC_CLKIN via PMUX0[29:27].
20 VSS2 power_in Ground pin 2 for the digital supply, paired with VDD2 and decoupled as shown in the datasheet power-pin figure.
21 VDD2 power_in Digital supply pin 2; operating voltage is 2.7 to 5.5 V and absolute maximum VDD is -0.3 to 6 V, decoupled to VSS2 with a 0.1 µF X7R capacitor placed close to the pins.
22 PB6 bidirectional Port B bit 6 GPIO, which powers up as GPIO and can alternatively be set to PWM1_CH6, PWM1_FLT0 or CAN_STDBY via PMUX2[8:6].
23 PB7 bidirectional Port B bit 7 GPIO, which powers up as GPIO and can alternatively be set to PWM1_CH3, ACMP_IN3 or I2C0_SCL via PMUX2[11:9].
24 PB8 bidirectional Port B bit 8 GPIO, which powers up as GPIO and can alternatively be set to PWM1_CH2, PWDT0_IN2 or I2C0_SDA via PMUX2[14:12].
25 PA10 bidirectional Port A bit 10 GPIO, which powers up as GPIO and can alternatively be set to PWM0_CH7, ADC_IN1/ACMP_IN1 or PWDT0_IN2 via PMUX1[2:0].
26 PA11 bidirectional Port A bit 11 GPIO, which powers up as GPIO and can alternatively be set to PWM0_CH6, ADC_IN0/ACMP_IN0 or PWDT0_IN1 via PMUX1[5:3].
27 PB9 bidirectional Port B bit 9 GPIO, which powers up as GPIO and can alternatively be set to PWM1_CH5, I2C1_SCL or UART2_TX via PMUX2[17:15].
28 PB10 bidirectional Port B bit 10 GPIO, which powers up as GPIO and can alternatively be set to PWM1_CH4, I2C1_SDA or UART2_RX via PMUX2[20:18].
29 PB2 bidirectional Port B bit 2 GPIO; its default function NMI_B1 is the non-maskable interrupt input, and PWM0_FLT0 and PWDT0_IN0 are also selectable via PMUX1[26:24].
30 PA13 bidirectional Port A bit 13 GPIO; its default function SWD_CLK1 is the serial wire debug clock (up to 20 MHz per Table 7-1), and EXT_CLKIN or RTC_CLKOUT can be selected via PMUX1[11:9].
31 RESET_B input External reset pin RESET_B; the shortest pulse it recognises as a reset request is 1.5 × t32k according to Table 6-4.
32 PA14 bidirectional Port A bit 14 GPIO; its default function SWD_DIO1 is the serial wire debug data line (input setup 5 ns and hold 5 ns per Table 7-1), and ACMP_OUT or PWM1_CH0 can be selected via PMUX1[14:12].
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer AutoChips
Package QFN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply voltage VDD -0.3 6 V 15
Maximum current flowing into VDD IDD 60 mA 15
Single-pin transient maximum current limit (all port pins) ID -20 20 mA 15
Storage temperature TSTG -55 150 °C 14
Soldering temperature, lead-free TSDR 260 °C 14
Electrostatic discharge voltage, human body model VHBM -4000 4000 V AEC-Q100-002-D 14
Electrostatic discharge voltage, charged device model VCDM -750 750 V AEC-Q100-011-C1 14
Latch-up current ILAT -100 100 mA 125 °C ambient, Class II, supply group 1.5 Vccmax (AEC-Q100-004-D) 14
Operating voltage 2.7 5.5 V 17
Operating temperature range (ambient) -40 125 °C 9
Flash program/erase operating voltage Vprog/erase 2.7 5.5 V -40 °C to 125 °C 27
Maximum total output high current, all ports IOHT 30 mA 5 V 17
Maximum total output high current, all ports IOHT 20 mA 3 V 17
Maximum total output low current, all ports IOLT 30 mA 5 V 17
Maximum total output low current, all ports IOLT 20 mA 3 V 17
Input leakage current per pin (high-impedance input) /IIn/ -1 0.1 1 µA VIN = VDD or VSS 17
Total input leakage current, all port pins /IINTOT/ 0 0.1 2 µA VIN = VDD or VSS, high-impedance input mode 17
Pull-up resistance RPU 40 75 190 kΩ All digital inputs with internal pull-up enabled 17
DC injection current, single pin IIC -2 2 mA VIN < VSS or VIN > VDD 18
RAM retention voltage VRAM 2 V 18
POR reset voltage VPOR 1.6 1.8 2 V 18
Falling-edge LVD threshold, low range VLVDL 2.5 2.6 2.7 V LVDV = 0 18
Falling-edge LVD threshold, high range VLVDH 4.05 4.2 4.35 V LVDV = 1 18
Falling-edge low-voltage warning threshold, high range VPVDH 4.45 4.6 4.75 V 18
Falling-edge low-voltage warning threshold, low range VPVDL 2.85 2.95 3.05 V 18
Buffered bandgap output VBG 1.19 1.2 1.21 V VDD = 5.0 V, Temp = 25 °C (factory-adjusted) 18
System and core clock frequency fSys 72 MHz 21
Bus clock frequency fBus 72 MHz 21
SWD_CLK operating frequency J1 0 20 MHz Full voltage range 25
SWD_CLK clock pulse width J3 20 ns Full voltage range 25
SWD_CLK rise and fall time J4 3 ns Full voltage range 25
SWD_DIO input data setup time before SWD_CLK rising J9 5 ns Full voltage range 25
SWD_DIO input data hold time after SWD_CLK rising J10 5 ns Full voltage range 25
SWD_CLK high to SWD_DIO data valid J11 41 ns Full voltage range 25
External oscillator frequency fhi 4 30 MHz Ambient -40 to 125 °C 25
LPOSC/LFOSC output frequency range flfosc 7.9 8 8.1 MHz Temperature range -40 °C to 125 °C 26
LPOSC factory-trimmed accuracy Δfint_ft -1.5 1.5 % T = 25 °C, VDD = 5 V 26
LPOSC frequency deviation over temperature Δfint_t -10 10 % Trimmed at T = 25 °C, VDD = 2.7-5.5 V; temperature range -40 °C to 125 °C 26
PLL input clock frequency fPLL_IN 4 30 MHz Operating ambient -40 to 125 °C 26
PLL output clock frequency fPLL_OUT 9 750 MHz Operating ambient -40 to 125 °C 26
VCO output frequency fVCO_OUT 500 1500 MHz Operating ambient -40 to 125 °C 26
ADC supply voltage VAVDD 2.7 5.5 V Absolute value 27
ADC buffered reference output VREF 1.35 2.75 V 27
ADC sampling time fsample 280 ns 28
Comparator supply voltage VAVDD 2.5 5.5 V 29
Comparator analog input offset voltage VAIO 40 mV 29
Filtered-out dominant CAN wake pulse tWUP 0.9 µs 31
Valid dominant CAN wake pulse tWUP 4.7 µs 31
Thermal resistance, junction-to-ambient, natural convection RθJA 37.36 °C/W 1S single-layer board (JESD51-2), natural convection 22
Thermal resistance, junction-to-ambient, natural convection RθJA 17.59 °C/W 2s2p four-layer board (JESD51-6), natural convection 22
Thermal resistance, junction-to-ambient, 200 ft/min airflow RθJMA 31.11 °C/W 1S single-layer board, 200 ft/min airflow 22
Thermal resistance, junction-to-ambient, 200 ft/min airflow RθJMA 13.72 °C/W 2s2p four-layer board, 200 ft/min airflow 22
Thermal resistance, junction-to-board RθJB 7.9 °C/W 1S single-layer board 23
Thermal resistance, junction-to-board RθJB 5.19 °C/W 2s2p four-layer board 23
Thermal resistance, junction-to-case (die to exposed pad) RθJC 27.08 °C/W 1S single-layer board 23
Thermal characteristic parameter, junction-to-package top center ΨJT 0.5 °C/W 1S single-layer board, natural convection 23
Thermal characteristic parameter, junction-to-package top center ΨJT 0.35 °C/W 2s2p four-layer board, natural convection 23
Thermal characteristic parameter, junction-to-package bottom center ΨJB 7.75 °C/W 1S single-layer board, natural convection 23
Thermal characteristic parameter, junction-to-package bottom center ΨJB 5.17 °C/W 2s2p four-layer board, natural convection 23

CAD (KiCad official)

  • Symbol: AC78013MDQA
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ac78013mdqa-etched.step / ac78013mdqa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ac78013mdqa.step / ac78013mdqa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: AutoChips datasheet (46 pp, sha256 35c60b3550508870, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF