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Contents

README

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AC6082A2

JieLi Tech · Digital Signal Processors (DSP/DSC) · SOP-16

AC6082A2 from JieLi Tech, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB7 bidirectional GPIO pin; configurable as SPI2 Data Out (A), Analog MUX1 Right, IIC SDA (C), ADC9, PWM5, or UART1 RX Data (A) with 24mA high or 8mA low drive capability.
2 PB6 bidirectional GPIO pin; configurable as SPI2 Clock (A), Analog MUX1 Left, IIC SCL (C), ADC8, Timer3 Clock Input, or UART1 TX Data (A) with 24mA high or 8mA low drive capability.
3 VSSIO power_in IO Ground (VSS); power and ground reference for IO circuits.
4 VBAT power_in Battery power supply input; recommended operating range 2.2V to 5.5V.
5 VDDIO power_in IO power supply; 3.3V output from internal LDO, supplies IO circuits.
6 PC5 bidirectional GPIO pin; configurable as SD0 Clock (A), SPI1 Data Out (B), IIC SDA (B), ADC12, Timer1 Clock Input, or UART2 RX Data (D) with 24mA high or 8mA low drive capability.
7 PC4 bidirectional GPIO pin; configurable as SD0 Command (A), SPI1 Clock (B), IIC SCL (B), ADC11, PWM1, or UART2 TX Data (D) with 24mA high or 8mA low drive capability.
8 PC3 bidirectional GPIO pin; configurable as SD0 Data (A), SPI1 Data In (B), Timer2 Capture, or UART0 TX/RX Data (D) with 24mA high or 8mA low drive capability.
9 USBDM bidirectional USB Negative Data line (D-); full-speed USB 2.0 OTG controller with 4mA drive and internal pull-down resistor (180 ohm).
10 USBDP bidirectional USB Positive Data line (D+); full-speed USB 2.0 OTG controller with 4mA drive and internal pull-down resistor (1.5 kilo-ohm).
11 PA2 bidirectional GPIO pin; configurable as Microphone Bias Output or Timer3 Capture with 24mA high or 8mA low drive capability.
12 PA1 bidirectional GPIO pin; configurable as Microphone Input Channel, ADC1, PWM4, or UART1 RX Data (C) with 24mA high or 8mA low drive capability.
13 PA0 bidirectional GPIO pin; configurable as SD Power Supply, ADC0, Clock Output 0, or UART1 TX Data (C); also provides DAC Right Channel (DACR) output function.
14 DACL output DAC Left Channel Output; 16-bit audio output with SNR ≥92dB and dynamic range 90dB.
15 AGND power_in Analog Ground (VSS); power and ground reference for analog circuits including DAC and ADC.
16 VCOM passive DAC Reference Voltage; external reference connection for DAC circuits.

Key specifications

Parameter Value
Manufacturer JieLi Tech
Package SOP-16
Category Embedded Processors & Controllers
Pins 16

CAD (KiCad official)

  • Symbol: AC6082A2
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: ac6082a2-etched.step / ac6082a2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ac6082a2.step / ac6082a2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: JieLi Tech datasheet (9 pp, sha256 a0563fb42cd9de5e, retrieved 2026-09-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF