component
AB1815-T3
Public Made by Adomby adom
Abracon LLC Real-time Clocks (RTC), QFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AB1815-T3
Abracon LLC · Real-time Clocks (RTC) · QFN-16(3x3)
AB1815-T3 from Abracon LLC, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | nRST | output | External reset output, open drain with polarity set by the RSP bit (active low on power up); needs an external pull-up if used and can float if unused. |
| 2 | WDI | input | Watchdog timer reset input that can also generate External 2 interrupt (EX2P/EX2E); has no internal pull, so it must not float and must be tied to VCC or VSS if unused. |
| 3 | nEXTR | input | External reset input that drives nRST to its asserted value when low and RS1E is set; no internal pull, so it must not float and must be tied to VCC or VSS if unused. |
| 4 | PSW/nIRQ2 | output | Secondary open-drain interrupt output (OUT2S configurable) that becomes a ~1 Ω power switch when PWR2 is set; can float if unused. |
| 5 | VBAT | power_in | Battery backup power connection; must be tied directly to VSS if no backup battery is present, and may also serve as the internal comparator analog input. |
| 6 | SDO | output | SPI data output connection. |
| 7 | SCL | input | Interface clock input for I2C and SPI parts; a pull-up resistor is required on this pin. |
| 8 | CLKOUT/nIRQ3 | output | Push-pull square wave output that can drive the OUT bit or the SQW square wave when SQWE is enabled. |
| 9 | SDI | input | SPI data input connection. |
| 10 | EXTI | input | External interrupt input (External 1 interrupt via EX1P/EX1E) with no internal pull, so it must not float and must be tied to VCC or VSS if unused. |
| 11 | FOUT/nIRQ | output | Primary open-drain interrupt/function output (OUT1S configurable) requiring an external pull-up, asserted low at power up until the device is accessible via the serial interface. |
| 12 | nCE | input | Active-low SPI chip select input; a pull-up resistor is recommended to avoid floating and inadvertent writes during power transitions. |
| 13 | VCC | power_in | Primary power connection; a single supply must be connected to VCC. |
| 14 | AF | passive | Autocalibration filter connection; place a 47 pF ceramic capacitor between this pin and VSS for improved Autocalibration timing accuracy. |
| 15 | XO | output | Crystal oscillator output connection. |
| 16 | XI | input | Crystal oscillator input connection. |
| 17 | VSS | power_in | Ground connection; the thermal pad (pin 17) on the bottom of the QFN-16 package must be connected to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Abracon LLC |
| Package | QFN-16(3x3) |
| Category | RTC/Clock Chip |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| System Power Voltage (abs max) | VCC | -0.3 | 3.8 | V | 10 | ||
| Battery Voltage (abs max) | VBAT | -0.3 | 3.8 | V | 10 | ||
| Input current | II | -10 | 10 | mA | 10 | ||
| Output current | IO | -20 | 20 | mA | 10 | ||
| PSW Output continuous current | IOPC | 50 | mA | 10 | |||
| PSW Output pulsed current | IOPP | 150 | mA | 1 second pulse | 10 | ||
| ESD Voltage CDM | VESD | -500 | 500 | V | CDM | 10 | |
| ESD Voltage HBM | VESD | -4000 | 4000 | V | HBM | 10 | |
| Latch-up Current | ILU | 100 | mA | 10 | |||
| Storage Temperature | TSTG | -55 | 125 | °C | 10 | ||
| Operating Temperature | TOP | -40 | 85 | °C | 10 | ||
| Lead temperature | TSLD | 300 | °C | Hand soldering for 10 seconds | 10 | ||
| Reflow soldering temperature | TREF | 260 | °C | Reflow profile per JEDEC J-STD-020D.1 | 10 | ||
| System Power Voltage | VCC | 1.5 | 3.6 | V | Static VCC Power, clocks operating and RAM and registers retained | 11 | |
| VCC I/O Interface Voltage | VCCIO | 1.5 | 3.6 | V | I2C or SPI operation | 11 | |
| VCC Start-up Voltage | VCCST | 1.6 | V | VCC Rising, POR -> VCC Power | 11 | ||
| VCC Switchover Threshold Hysteresis | VCCSWH | 70 | mV | VCC Power <-> VBAT Power | 11 | ||
| Battery Voltage | VBAT | 1.4 | 3.6 | V | Static VBAT Power, clocks operating and RAM and registers retained | 11 | |
| Battery Switchover Voltage Range | VBATSW | 1.6 | 3.6 | V | VCC Power -> VBAT Power | 11 | |
| Positive-going Input Threshold Voltage | VT+ | 1.5 | 2 | V | VCC = 3.0V | 13 | |
| Positive-going Input Threshold Voltage | VT+ | 1.1 | 1.25 | V | VCC = 1.8V | 13 | |
| Negative-going Input Threshold Voltage | VT- | 0.8 | 0.9 | V | VCC = 3.0V | 13 | |
| Negative-going Input Threshold Voltage | VT- | 0.5 | 0.6 | V | VCC = 1.8V | 13 | |
| Input leakage current | IILEAK | 0.02 | 80 | nA | VCC = 3.0V | 13 | |
| High level output current on push-pull outputs | IOH | -2 | -3.8 | mA | VOH = 0.8●VCC, VCC = 1.7V | 13 | |
| High level output current on push-pull outputs | IOH | -7 | -11 | mA | VOH = 0.8●VCC, VCC = 3.0V | 13 | |
| Low level output current | IOL | 3.3 | 5.9 | mA | VOL = 0.2●VCC, VCC = 1.7V | 13 | |
| Low level output current | IOL | 17 | 19 | mA | VOL = 0.2●VCC, VCC = 3.0V | 13 | |
| PSW output resistance to VSS | RDSON | 1.1 | 3.8 | Ω | PSW Enabled, VCC = 3.0V | 13 | |
| PSW output resistance to VSS | RDSON | 1.7 | 5.8 | Ω | PSW Enabled, VCC = 1.7V | 13 | |
| Output leakage current | IOLEAK | 0.02 | 80 | nA | VCC = 1.7V, 3.6V | 13 | |
| Uncalibrated RC Oscillator Frequency | FRCU | 89 | 122 | 220 | Hz | Calibration Disabled (OFFSETR = 0) | 14 |
| XT Crystal Frequency | FXT | 32.768 | kHz | 14 | |||
| Calibrated RC Oscillator Frequency | FRCC | 128 | Hz | Factory Calibrated at 25°C, VCC = 2.8V | 14 | ||
| RC Oscillator cycle-to-cycle jitter | JRCCC | 2000 | ppm | Calibration Disabled (OFFSETR = 0), 128 Hz | 14 | ||
| RC Oscillator cycle-to-cycle jitter | JRCCC | 500 | ppm | Calibration Disabled (OFFSETR = 0), 1 Hz | 14 | ||
| XT mode digital calibration accuracy | AXT | -2 | 2 | ppm | Calibrated at an initial temperature and voltage | 14 | |
| Autocalibration timing accuracy | AAC | 35 | ppm | 24 hour run time, 512 second period, TA = -10°C to 60°C | 14 | ||
| Autocalibration timing accuracy | AAC | 20 | ppm | 1 week run time, 512 second period, TA = -10°C to 60°C | 14 | ||
| Autocalibration timing accuracy | AAC | 10 | ppm | 1 month run time, 512 second period, TA = -10°C to 60°C | 14 | ||
| Autocalibration timing accuracy | AAC | 3 | ppm | 1 year run time, 512 second period, TA = -10°C to 60°C | 14 | ||
| Autocalibration mode operating temperature | TAC | -10 | 60 | °C | 14 | ||
| VBAT falling threshold | VBRF | 2.3 | 2.5 | 3.3 | V | BREF = 0111 | 24 |
| VBAT falling threshold | VBRF | 1.9 | 2.1 | 2.8 | V | BREF = 1011 | 24 |
| VBAT falling threshold | VBRF | 1.6 | 1.8 | 2.5 | V | BREF = 1101 | 24 |
| VBAT rising threshold | VBRR | 2.6 | 3 | 3.4 | V | BREF = 0111 | 24 |
| VBAT rising threshold | VBRR | 2.1 | 2.5 | 2.9 | V | BREF = 1011 | 24 |
| VBAT rising threshold | VBRR | 1.9 | 2.2 | 2.7 | V | BREF = 1101 | 24 |
| VBAT analog comparator recommended operating temperature range | TBR | -20 | 70 | °C | All values | 24 | |
| SCL input clock frequency (I2C) | fSCL | 10 | 400 | kHz | VCC 1.7V-3.6V | 25 | |
| Low period of SCL clock | tLOW | 1.3 | µs | VCC 1.7V-3.6V | 25 | ||
| High period of SCL clock | tHIGH | 600 | ns | VCC 1.7V-3.6V | 25 | ||
| Rise time of SDA and SCL | tRISE | 300 | ns | VCC 1.7V-3.6V | 25 | ||
| Fall time of SDA and SCL | tFALL | 300 | ns | VCC 1.7V-3.6V | 25 | ||
| SDA setup time | tSU:DAT | 100 | ns | VCC 1.7V-3.6V | 25 | ||
| Bus free time before a new transmission | tBUF | 1.3 | µs | VCC 1.7V-3.6V | 25 | ||
| SCL input clock frequency (SPI) | fSCL | 0.01 | 2 | MHz | VCC 1.7V-3.6V | 27 | |
| SDI setup time | tSU:SDI | 40 | ns | VCC 1.7V-3.6V | 27 | ||
| SDO output Hi-Z from nCE | tHZ | 250 | ns | VCC 1.7V-3.6V | 27 |
CAD (KiCad official)
- Symbol:
AB1815-T3 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ab1815-t3-etched.step/ab1815-t3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ab1815-t3.step/ab1815-t3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Abracon LLC datasheet (37 pp, sha256
8f5073f018cbaa67, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AB1815-T3
**Abracon LLC** · Real-time Clocks (RTC) · QFN-16(3x3)
AB1815-T3 from Abracon LLC, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | nRST | output | External reset output, open drain with polarity set by the RSP bit (active low on power up); needs an external pull-up if used and can float if unused. |
| 2 | WDI | input | Watchdog timer reset input that can also generate External 2 interrupt (EX2P/EX2E); has no internal pull, so it must not float and must be tied to VCC or VSS if unused. |
| 3 | nEXTR | input | External reset input that drives nRST to its asserted value when low and RS1E is set; no internal pull, so it must not float and must be tied to VCC or VSS if unused. |
| 4 | PSW/nIRQ2 | output | Secondary open-drain interrupt output (OUT2S configurable) that becomes a ~1 Ω power switch when PWR2 is set; can float if unused. |
| 5 | VBAT | power_in | Battery backup power connection; must be tied directly to VSS if no backup battery is present, and may also serve as the internal comparator analog input. |
| 6 | SDO | output | SPI data output connection. |
| 7 | SCL | input | Interface clock input for I2C and SPI parts; a pull-up resistor is required on this pin. |
| 8 | CLKOUT/nIRQ3 | output | Push-pull square wave output that can drive the OUT bit or the SQW square wave when SQWE is enabled. |
| 9 | SDI | input | SPI data input connection. |
| 10 | EXTI | input | External interrupt input (External 1 interrupt via EX1P/EX1E) with no internal pull, so it must not float and must be tied to VCC or VSS if unused. |
| 11 | FOUT/nIRQ | output | Primary open-drain interrupt/function output (OUT1S configurable) requiring an external pull-up, asserted low at power up until the device is accessible via the serial interface. |
| 12 | nCE | input | Active-low SPI chip select input; a pull-up resistor is recommended to avoid floating and inadvertent writes during power transitions. |
| 13 | VCC | power_in | Primary power connection; a single supply must be connected to VCC. |
| 14 | AF | passive | Autocalibration filter connection; place a 47 pF ceramic capacitor between this pin and VSS for improved Autocalibration timing accuracy. |
| 15 | XO | output | Crystal oscillator output connection. |
| 16 | XI | input | Crystal oscillator input connection. |
| 17 | VSS | power_in | Ground connection; the thermal pad (pin 17) on the bottom of the QFN-16 package must be connected to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Abracon LLC |
| Package | QFN-16(3x3) |
| Category | RTC/Clock Chip |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| System Power Voltage (abs max) | VCC | -0.3 | | 3.8 | V | | 10 |
| Battery Voltage (abs max) | VBAT | -0.3 | | 3.8 | V | | 10 |
| Input current | II | -10 | | 10 | mA | | 10 |
| Output current | IO | -20 | | 20 | mA | | 10 |
| PSW Output continuous current | IOPC | | | 50 | mA | | 10 |
| PSW Output pulsed current | IOPP | | | 150 | mA | 1 second pulse | 10 |
| ESD Voltage CDM | VESD | -500 | | 500 | V | CDM | 10 |
| ESD Voltage HBM | VESD | -4000 | | 4000 | V | HBM | 10 |
| Latch-up Current | ILU | | | 100 | mA | | 10 |
| Storage Temperature | TSTG | -55 | | 125 | °C | | 10 |
| Operating Temperature | TOP | -40 | | 85 | °C | | 10 |
| Lead temperature | TSLD | | | 300 | °C | Hand soldering for 10 seconds | 10 |
| Reflow soldering temperature | TREF | | | 260 | °C | Reflow profile per JEDEC J-STD-020D.1 | 10 |
| System Power Voltage | VCC | 1.5 | | 3.6 | V | Static VCC Power, clocks operating and RAM and registers retained | 11 |
| VCC I/O Interface Voltage | VCCIO | 1.5 | | 3.6 | V | I2C or SPI operation | 11 |
| VCC Start-up Voltage | VCCST | | | 1.6 | V | VCC Rising, POR -> VCC Power | 11 |
| VCC Switchover Threshold Hysteresis | VCCSWH | | 70 | | mV | VCC Power <-> VBAT Power | 11 |
| Battery Voltage | VBAT | 1.4 | | 3.6 | V | Static VBAT Power, clocks operating and RAM and registers retained | 11 |
| Battery Switchover Voltage Range | VBATSW | 1.6 | | 3.6 | V | VCC Power -> VBAT Power | 11 |
| Positive-going Input Threshold Voltage | VT+ | 1.5 | | 2 | V | VCC = 3.0V | 13 |
| Positive-going Input Threshold Voltage | VT+ | 1.1 | | 1.25 | V | VCC = 1.8V | 13 |
| Negative-going Input Threshold Voltage | VT- | 0.8 | | 0.9 | V | VCC = 3.0V | 13 |
| Negative-going Input Threshold Voltage | VT- | 0.5 | | 0.6 | V | VCC = 1.8V | 13 |
| Input leakage current | IILEAK | | 0.02 | 80 | nA | VCC = 3.0V | 13 |
| High level output current on push-pull outputs | IOH | -2 | -3.8 | | mA | VOH = 0.8●VCC, VCC = 1.7V | 13 |
| High level output current on push-pull outputs | IOH | -7 | -11 | | mA | VOH = 0.8●VCC, VCC = 3.0V | 13 |
| Low level output current | IOL | 3.3 | 5.9 | | mA | VOL = 0.2●VCC, VCC = 1.7V | 13 |
| Low level output current | IOL | 17 | 19 | | mA | VOL = 0.2●VCC, VCC = 3.0V | 13 |
| PSW output resistance to VSS | RDSON | | 1.1 | 3.8 | Ω | PSW Enabled, VCC = 3.0V | 13 |
| PSW output resistance to VSS | RDSON | | 1.7 | 5.8 | Ω | PSW Enabled, VCC = 1.7V | 13 |
| Output leakage current | IOLEAK | | 0.02 | 80 | nA | VCC = 1.7V, 3.6V | 13 |
| Uncalibrated RC Oscillator Frequency | FRCU | 89 | 122 | 220 | Hz | Calibration Disabled (OFFSETR = 0) | 14 |
| XT Crystal Frequency | FXT | | 32.768 | | kHz | | 14 |
| Calibrated RC Oscillator Frequency | FRCC | | 128 | | Hz | Factory Calibrated at 25°C, VCC = 2.8V | 14 |
| RC Oscillator cycle-to-cycle jitter | JRCCC | | | 2000 | ppm | Calibration Disabled (OFFSETR = 0), 128 Hz | 14 |
| RC Oscillator cycle-to-cycle jitter | JRCCC | | | 500 | ppm | Calibration Disabled (OFFSETR = 0), 1 Hz | 14 |
| XT mode digital calibration accuracy | AXT | -2 | | 2 | ppm | Calibrated at an initial temperature and voltage | 14 |
| Autocalibration timing accuracy | AAC | | | 35 | ppm | 24 hour run time, 512 second period, TA = -10°C to 60°C | 14 |
| Autocalibration timing accuracy | AAC | | | 20 | ppm | 1 week run time, 512 second period, TA = -10°C to 60°C | 14 |
| Autocalibration timing accuracy | AAC | | | 10 | ppm | 1 month run time, 512 second period, TA = -10°C to 60°C | 14 |
| Autocalibration timing accuracy | AAC | | | 3 | ppm | 1 year run time, 512 second period, TA = -10°C to 60°C | 14 |
| Autocalibration mode operating temperature | TAC | -10 | | 60 | °C | | 14 |
| VBAT falling threshold | VBRF | 2.3 | 2.5 | 3.3 | V | BREF = 0111 | 24 |
| VBAT falling threshold | VBRF | 1.9 | 2.1 | 2.8 | V | BREF = 1011 | 24 |
| VBAT falling threshold | VBRF | 1.6 | 1.8 | 2.5 | V | BREF = 1101 | 24 |
| VBAT rising threshold | VBRR | 2.6 | 3 | 3.4 | V | BREF = 0111 | 24 |
| VBAT rising threshold | VBRR | 2.1 | 2.5 | 2.9 | V | BREF = 1011 | 24 |
| VBAT rising threshold | VBRR | 1.9 | 2.2 | 2.7 | V | BREF = 1101 | 24 |
| VBAT analog comparator recommended operating temperature range | TBR | -20 | | 70 | °C | All values | 24 |
| SCL input clock frequency (I2C) | fSCL | 10 | | 400 | kHz | VCC 1.7V-3.6V | 25 |
| Low period of SCL clock | tLOW | 1.3 | | | µs | VCC 1.7V-3.6V | 25 |
| High period of SCL clock | tHIGH | 600 | | | ns | VCC 1.7V-3.6V | 25 |
| Rise time of SDA and SCL | tRISE | | | 300 | ns | VCC 1.7V-3.6V | 25 |
| Fall time of SDA and SCL | tFALL | | | 300 | ns | VCC 1.7V-3.6V | 25 |
| SDA setup time | tSU:DAT | 100 | | | ns | VCC 1.7V-3.6V | 25 |
| Bus free time before a new transmission | tBUF | 1.3 | | | µs | VCC 1.7V-3.6V | 25 |
| SCL input clock frequency (SPI) | fSCL | 0.01 | | 2 | MHz | VCC 1.7V-3.6V | 27 |
| SDI setup time | tSU:SDI | 40 | | | ns | VCC 1.7V-3.6V | 27 |
| SDO output Hi-Z from nCE | tHZ | | | 250 | ns | VCC 1.7V-3.6V | 27 |
## CAD (KiCad official)
- Symbol: `AB1815-T3`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `ab1815-t3-etched.step` / `ab1815-t3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ab1815-t3.step` / `ab1815-t3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Abracon LLC datasheet](docs/ab1815-t3-datasheet.pdf) (37 pp, sha256 `8f5073f018cbaa67`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ab1815-t3-datasheet.pdf)