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AAS33001LLEATR-5
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Allegro MicroSystems, LLC Position Sensor, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAAS33001LLEATR-5
Allegro MicroSystems, LLC · Position Sensor · TSSOP-14
AAS33001LLEATR-5 from Allegro MicroSystems, LLC, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BYP_1 | passive | External bypass capacitor terminal for the internal regulator (die 1), specified with CBYP = 0.1 µF. |
| 2 | VCC_1 | power_in | Power supply terminal; supply voltage range is 3.7 to 18 V, with 28 V absolute maximum continuous. |
| 3 | TEST_1 | passive | Connect to ground (die 1). |
| 4 | PWM_1 | output | PWM angle output (die 1); the output low clamp is 5% and the high clamp is 95% duty cycle. |
| 5 | GND | power_in | Device ground terminal. |
| 6 | GND | power_in | Device ground terminal. |
| 7 | GND | power_in | Device ground terminal. |
| 8 | CS_1 | input | SPI chip select terminal, active-low input (die 1); also used for address selection for the Manchester interface. |
| 9 | SCLK_1 | input | SPI clock terminal input (die 1); SPI clock frequency is specified from 0.1 to 10 MHz. |
| 10 | MOSI_1 | input | SPI master output / slave input (die 1); also used for address selection for the Manchester interface. |
| 11 | MISO_1 | output | SPI master input / slave output (die 1); for the 5.0 V interface, VOH is 4.0 to 5.5 V and VOL is 0.3 V typical at CL = 20 pF maximum. |
| 12 | A_1/U_1 | output | Option 1: quadrature A output signal (die 1). Option 2: U (phase 1) output signal (die 1). |
| 13 | B_1/V_1 | output | Option 1: quadrature B output signal (die 1). Option 2: V (phase 2) output signal (die 1). |
| 14 | I_1/W_1 | output | Option 1: quadrature I (index) output signal (die 1). Option 2: W (phase 3) output signal (die 1). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | TSSOP-14 |
| Category | Sensors |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 3.7 | 18 | V | 5 | ||
| Supply Current (single die) | ICC(full) | 15 | 19 | mA | For single die | 5 | |
| Power-On Reset Threshold Voltage (rising) | VPORHI | 3.7 | V | VCC rising, dV/dt = 1 V/ms, TA = 25°C | 5 | ||
| Power-On Reset Threshold Voltage (falling) | VPORLOW | 3.3 | V | VCC falling, dV/dt = 1 V/ms, TA = 25°C | 5 | ||
| Undervoltage Warning Level | VUV | 3.7 | 3.82 | 4 | V | TA = -40°C to 150°C | 5 |
| Supply Zener Clamp Voltage | VZSUP | 26.5 | V | ICC = ICC(AWAKE) + 3 mA, TA = 25°C | 5 | ||
| Reverse Battery Current | IRCC | 5 | mA | VRCC = -18 V, TA = 25°C | 5 | ||
| Bypass Pin Output Voltage (5.0 V interface) | VBYP | 4 | 5 | 5.5 | V | TA = 25°C, CBYP = 0.1 µF, 5.0 V interface enabled and VCC ≥ 5.0 V | 5 |
| Digital Input High Voltage (5.0 V interface) | VIH | 3.75 | 5.5 | V | MOSI, SCLK, CS pins | 5 | |
| Digital Input Low Voltage (5.0 V interface) | VIL | 0.5 | V | MOSI, SCLK, CS pins | 5 | ||
| Output High Voltage (5.0 V interface) | VOH | 4 | 5 | 5.5 | V | MISO and ABI/UVW pins, CL = 20 pF, TA = 25°C, VCC ≥ 5.0 V | 5 |
| SPI Clock Frequency | fSCLK | 0.1 | 10 | MHz | MISOx pins, CL = 20 pF | 5 | |
| SPI Clock Duty Cycle | DfSCLK | 40 | 60 | % | 5 | ||
| SPI Frame Rate | tSPI | 5.8 | 588 | kHz | 5 | ||
| Chip Select to First SCLK Edge | tCS | 50 | ns | Time from CSx going low to SCLKx falling edge | 5 | ||
| Chip Select Inactive Time | tCSH | 150 | ns | Time in which CSx is held high before the next frame | 5 | ||
| Data Output Valid Time | tDAV | 50 | ns | Data output valid after SCLKx falling edge | 5 | ||
| MOSI Setup Time | tSU | 25 | ns | Input setup time before SCLKx rising edge | 5 | ||
| MOSI Hold Time | tHD | 50 | ns | Input hold time after SCLKx rising edge | 5 | ||
| SCLK to CS Hold Time | tCHD | 5 | ns | Hold SCLKx high time before CSx rising edge | 5 | ||
| Load Capacitance | CL | 20 | pF | Loading on digital output (MISOx) pin | 5 | ||
| ABI and UVW Output Angular Hysteresis | hysANG | 0 | 1.38 | degrees | Programmable | 6 | |
| Manchester High Voltage | VMAN(H) | 7.3 | 8 | V | Applied to VCC line | 6 | |
| Manchester Low Voltage | VMAN(L) | 5 | 5.7 | V | Applied to VCC line | 6 | |
| Manchester Bitrate | fMAN | 2.2 | 100 | kbit/s | Line state changes once or twice per bit | 6 | |
| Magnetic Field B Range | B | 1200 | G | Range of input field | 6 | ||
| Angle Error at 25°C | ERRANG | -1 | 0.4 | 1 | degrees | TA = 25°C, ideal magnet alignment, B = 300 G, target rpm = 0 | 7 |
| Angle Error at 150°C | ERRANG | -1.3 | 0.7 | 1.3 | degrees | TA = 150°C, ideal magnet alignment, B = 300 G, target rpm = 0 | 7 |
| Temperature Drift (150°C) | ANGLEDRIFT | -1.4 | 1.4 | degrees | TA = 150°C, B = 300 G, angle change from 25°C | 7 | |
| Forward Supply Voltage | VCC | 28 | V | Sampling angles, respecting TJ(max) | 3 | ||
| Reverse Supply Voltage | VRCC | -18 | V | Not sampling angles | 3 | ||
| All Other Pins Forward Voltage | VIN | 5.5 | V | 3 | |||
| All Other Pins Reverse Voltage | VR | 0.5 | V | All other pins reverse voltage | 3 | ||
| Operating Ambient Temperature | TA | -40 | 150 | °C | L range | 3 | |
| Maximum Junction Temperature | TJ(max) | 170 | °C | 3 | |||
| Storage Temperature | Tstg | -65 | 170 | °C | 3 | ||
| Package Thermal Resistance (LE-14) | RθJA | 82 | °C/W | LE-14 package; measured on JEDEC JESD51-7 2s2p board | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | a single-die 14-pin TSSOP package. The packages are lead (Pb) free with 100% matte-tin leadframe plating. The 1 mm | 1 |
CAD (KiCad official)
- Symbol:
AAS33001LLEATR-5 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
aas33001lleatr-5-etched.step/aas33001lleatr-5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aas33001lleatr-5.step/aas33001lleatr-5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (63 pp, sha256
9396523e775a8b3e, retrieved 2026-10-29, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).