component
A96G174FDN
Public Made by Adomby adom
ABOV Semicon Microcontrollers (MCU/MPU/SOC), SOP-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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{
"number": "4",
"name": "P02",
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"description": "Port 0 bit 2 I/O, shared with RESETB active-low reset input with pull-up on A96G174, EINT0 external interrupt ch-0 and SCL I2C clock."
},
{
"number": "5",
"name": "P03",
"type": "bidirectional",
"description": "Port 0 bit 3 I/O, shared with AN5 ADC input ch-5, T0O Timer 0 interval output and PWM0O Timer 0 PWM output."
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{
"number": "6",
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"description": "Port 0 bit 4 I/O, shared with AN6 ADC input ch-6, T2O Timer 2 interval output and PWM2O Timer 2 PWM output."
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{
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"description": "Port 0 bit 6 I/O, shared with AN8 ADC input ch-8, MOSI(TXD) USART transmit/SPI MOSI and PWM1OB Timer 1 complementary PWM output."
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{
"number": "9",
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"description": "Port 0 bit 7 I/O, shared with AN9 ADC input ch-9, MISO(RXD) USART receive/SPI MISO, T1O Timer 1 interval output and PWM1O Timer 1 PWM output."
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{
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{
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"description": "Port 1 bit 3 I/O, shared with AN11 ADC input ch-11, EINT1 external interrupt ch-1, EC1 Timer 1 event capture input and XCK USART clock."
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{
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"type": "bidirectional",
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"description": "Port 1 bit 5 I/O, shared with AN13 ADC input ch-13, EINT2 external interrupt ch-2 and RXD(MISO) USART receive/SPI MISO."
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{
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"type": "bidirectional",
"description": "Port 1 bit 6 I/O, shared with AN14 ADC input ch-14 (RESETB function applies to A96S174 only)."
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"description": "Port 1 bit 7 I/O, shared with AN0 ADC input ch-0 and PWM1OB Timer 1 PWM complementary output."
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{
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"name": "P20",
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"description": "Port 2 bit 0 I/O, shared with AN1 ADC input ch-1, T1O Timer 1 interval output and PWM1O Timer 1 PWM output."
},
{
"number": "19",
"name": "P21",
"type": "bidirectional",
"description": "Port 2 bit 1 I/O, shared with AN2 ADC input ch-2."
},
{
"number": "20",
"name": "VSS",
"type": "power_in",
"description": "Ground pin."
}
],
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"vision extraction: provenance cannot be text-verified; needs consensus"
],
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"at": "2026-11-04T18:11:03"
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"appearance": {
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{
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"typ": 4,
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"conditions": "AVDD = 5.0V; MCLK = 8MHz",
"source_page": 62,
"source": "datasheet"
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{
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{
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{
"name": "ADC operating current (enabled)",
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{
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{
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{
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{
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{
"name": "LVR/LVI detection level",
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{
"name": "LVR/LVI detection level",
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{
"name": "LVR/LVI hysteresis",
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{
"name": "LVR and LVI current (both enabled)",
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{
"name": "LVR and LVI current (one of two enabled)",
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{
"name": "LVR and LVI current (both disabled)",
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{
"name": "High internal RC oscillator tolerance",
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"name": "High internal RC oscillator tolerance",
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