component

A8653KLPTR-T

Public Made by Adom

by adom

Allegro MicroSystems, LLC DC-DC Converters, HTSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chipa8653klptr-tfactory-2.0.0extractor-text

Verified A8653KLPTR-T

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: A8653KLPTR-T · HTSSOP-16 · 17 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 37-page datasheet
  • ✓distributor: lcsc C2071733, digikey 620-A8653KLPTR-TTR-ND, mouser 250-A8653KLPTR-T
  • ✓family: TSSOP-16-1EP_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-eiwfuyz0/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.36)
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ a8653klptr-t.kicad_sym✓ a8653klptr-t.kicad_mod✓ a8653klptr-t.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers a8653klptr-t: viewers · Ray 3d ago
a8653klptr-t-etched.glb Publish 0.1.0 · Ray 3d ago
a8653klptr-t-etched.step a8653klptr-t: factory component page (tier=lcsc) · Ray 3d ago
a8653klptr-t-hero.glb a8653klptr-t: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
a8653klptr-t-hero.overlay.json Publish 0.1.0 · Ray 3d ago
a8653klptr-t.glb Publish 0.1.0 · Ray 3d ago
a8653klptr-t.kicad_mod Publish 0.1.0 · Ray 3d ago
a8653klptr-t.kicad_sym Publish 0.1.0 · Ray 3d ago
a8653klptr-t.lbr Publish 0.1.0 · Ray 3d ago
a8653klptr-t.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
verification.json Verified: Published by the parts factory: tier lcsc, 17 pins · Ray 3d ago

A8653KLPTR-T

Allegro MicroSystems, LLC · DC-DC Converters · HTSSOP-16

A8653KLPTR-T from Allegro MicroSystems, LLC, in a HTSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input: set high to turn the converter on or set low to turn it off; it may be connected to VIN.
2 VIN power_in Power input for the control circuits and the drain of the internal high-side N-channel MOSFET; a high-quality ceramic capacitor should be placed very close to this pin.
3 SS passive Soft-start pin; a capacitor CSS from this pin to GND sets the soft-start time and also determines the hiccup period during overcurrent.
4 GADJ input Sets the gain of the differential current sense amplifier via a resistor to GND; grounding GADJ disables the Remote Load Regulation function.
5 FB input Feedback (negative) input to the error amplifier; a resistor divider from the converter output (VOUT) programs the output voltage.
6 IADJ input Active current limit adjust pin; a resistor from this pin to GND sets the current limit, and when load current exceeds it the output voltage decreases at a predefined slope.
7 SGND power_in Signal (quiet) ground.
8 COMP passive Output of the error amplifier and loop compensation node; a series RC network from this pin to GND compensates the control loop.
9 SYNC/FSET input Frequency setting and synchronization pin; a resistor RFSET from this pin to GND sets the PWM switching frequency.
10 POK output Power OK open-drain output that transitions from low to high impedance when the output is within the final regulation voltage and no load-side current limit exists.
11 ISEN- input Negative current-sensing pin to the internal current sense amplifier, connected to the load side of the external current sensing resistor.
12 ISEN+ input Positive current-sensing pin to the internal current sense amplifier, connected to the inductor side of the external current sensing resistor.
13 PGND power_in Power ground.
14 PGND power_in Power ground.
15 SW output Source of the high-side N-channel MOSFET; the output inductor LO connects to this pin and should be placed as close as possible with relatively wide traces.
16 BOOT passive High-side gate drive boost input; connect a 100 nF ceramic capacitor from BOOT to SW.
17 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package HTSSOP-16
Category Power Supply Chip
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN, EN, SS -0.3 40 V 3
SW to GND VSW -0.3 V Continuous; upper limit printed as VIN + 0.3 V 3
SW to GND VSW -1 V VIN ≤ 36 V, t < 50 ns; upper limit printed as VIN + 2 V 3
BOOT Pin Above SW Pin VBOOT -0.3 5.5 V Continuous, above SW pin (VSW, 0.3 to VSW + 5.5 V) 3
BOOT Pin Above SW Pin VBOOT -0.3 7 V < 1 ms, above SW pin (VSW, 0.3 to VSW + 7 V) 3
ISEN+ and ISEN- Pins -0.3 6.5 V 3
ISEN+ to ISEN- Differential Voltage -0.3 0.3 V 3
All other pins -0.3 5.5 V 3
Maximum Junction Temperature TJ(max) 150 ºC 3
Storage Temperature Range Tstg -55 150 ºC 3
Operating Input Voltage Range VIN 4 36 V 6
Output Voltage Setting Range VOUT 3.3 5.75 V 6
Current sense resistor (Rsen) Rsen 20 50 mΩ Load-side current sense resistor value 13
GADJ equivalent resistance range RG_eqv 10 34 kΩ Eq. 7: 10 kΩ < RG_eqv < 34 kΩ 15
IADJ equivalent resistance range RI_eqv 10 34 kΩ Eq. 8: 10 kΩ < RI_eqv < 34 kΩ 15
Output capacitor charge current during soft-start (recommended) ICO 0.1 0.3 A Recommended 0.1 A < ICO < 0.3 A 27
UVLO Start Threshold VUVLO(START) 3.4 3.7 V VIN rising 6
UVLO Stop Threshold VUVLO(STOP) 2.6 2.9 V VIN falling 6
Input Quiescent Current IQ 3 6.5 mA VEN = 5 V, VFB = 1 V, no PWM switching 6
Input Sleep Supply Current IQSLEEP 1 240 µA VIN = 12 V, VEN ≤ 0.4 V, -40°C < TA = TJ < 85°C 6
Input Sleep Supply Current IQSLEEP 40 900 µA VIN = 12 V, VEN ≤ 0.4 V, TA = TJ = 125°C 6
Feedback Voltage Accuracy VFB 792 800 808 mV VFB = VCOMP, VGADJ = 0 V, -40°C < TA = TJ < 125°C 6
Feedback Voltage Accuracy VFB 788 800 812 mV VFB = VCOMP, VGADJ = 0 V 6
Feedback Voltage Accuracy with Cable Compensation VFB(ACC) 808 825 842 mV VFB = VCOMP, VISEN+, VISEN- = 25 mV, VOUT = 5 V, RGADJ = 20 kΩ, RIADJ = 20 kΩ 6
Error Amp Clamp Voltage VFB(CLAMP) 900 920 940 mV VFB = VCOMP, VISEN+, VISEN- = 55 mV, VOUT =5 V, RGADJ = 7.5 kΩ, RIADJ = 20 kΩ 6
Output Dropout Voltage VO(PWM) 4.9 V VIN = 5.7 V, IO = 2.6 A, fSW = 500 kHz (A8653) 6
Feedback Input Bias Current IFB -100 -8 nA 6
Transconductance gmEA 550 750 950 µA/V 400 mV < VFB 6
Transconductance gmEA 275 375 475 µA/V 0 V < VFB < 400 mV 6
Output Current IEA -75 75 µA VCOMP = 1.2 V (printed as ±75 µA) 6
SW Leakage ISW(LEAK) -10 0 10 µA VEN ≤ 0.4 V, VSW = 5 V, VIN = 12 V, TJ = 25°C 6
PWM Switching Frequency fSW 375 415 457 kHz RFSET = 61.9 kΩ 7
PWM Frequency Dithering fDITHER -13 13 % No dithering with FSET synchronization (printed as ±13 %) 7
Minimum Controllable On-Time tON(MIN) 95 135 ns VIN = 12 V, IOUT = 1 A 7
Minimum Switch Off-Time tOFF(MIN) 100 135 ns VIN = 12 V, IOUT = 1 A 7
Synchronization Frequency Range fSW_MULT 100 2200 kHz 7
Synchronization Input Off-Time tSYNC_OFF 0.2 1.3 µs 7
Synchronization Input Rise Time tr(SYNC) 10 15 ns 7
Synchronization Input Fall Time tf(SYNC) 10 15 ns 7
Synchronization Rising Threshold VSYNC(HI) 2 V VSYNC rising 7
Synchronization Falling Threshold VSYNC(LO) 0.5 0.7 V VSYNC falling 7
Peak Inductor (Pulse-by-Pulse) Current Limit IPK_LIM(MINON) 3.3 4 4.62 A tON = tON(MIN) (A8653) 7
Peak Inductor (Pulse-by-Pulse) Current Limit IPK_LIM(MINOFF) 2.4 3.2 4 A tON = 1/fSW, tOFF(MIN), No Sync (A8653) 7
Load-Side Current Limit IOUT_LIM 2.5 3 3.3 A RIADJ = 20 kΩ, RSEN = 20 mΩ, VOUT = 5 V (A8653) 7
Slope Compensation SE 0.09 0.24 0.43 A/µs RFSET = 61.9 kΩ, 415 kHz (A8653) 7
SS FAULT/HICCUP Reset Voltage VSS(RST) 200 275 mV VSS falling due to RSS(FLT) 8
SS Startup (Source) Current ISS(SU) -30 -20 -10 µA HICCUP = FAULT = 0 8
SS Hiccup (Sink) Current ISS(HIC) 1 2.2 5 µA HICCUP = 1 8
POK Output Voltage VPOK 0.4 V IPOK = 4 mA 8
POK Leakage IPOK(LEAK) 5 µA VPOK = 5 V 8
POK UV Threshold VPOK(UV) 715 740 760 mV VFB falling 8
POK OV Threshold VPOK(OV) 840 880 920 mV VFB rising, VGADJ = 0 V 8
POK OV Threshold VPOK(OV) 865 905 950 mV VFB rising, VISEN+, VISEN- = 25 mV, VOUT = 5 V, RGADJ = 20 kΩ, RIADJ = 20 kΩ 8
ISEN+ OV Threshold VISEN(OV) 5.4 5.65 6 V ISEN+ rising, VGADJ = 0 V 8
ISEN+ OV Threshold VISEN(OV) 5.6 5.8 6.1 V ISEN+ rising, VISEN+, VISEN- = 25 mV, VOUT = 5 V, RGADJ = 20 kΩ, RIADJ = 20 kΩ 8
TSD Rising Threshold TSD 155 170 185 ºC PWM stops immediately and COMP is pulled low and SS is reset 8
EN High Threshold VEN(H) 1.41 2 V EN rising 9
EN Low Threshold VEN(L) 0.7 1.36 V EN falling 9
Package Thermal Resistance RθJA 34 ºC/W LP Package, 4-layer PCB based on JEDEC standard 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin exposed pads for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte-tin lead frame plating. The maximum junction 2

CAD (KiCad official)

  • Symbol: A8653KLPTR-T
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: a8653klptr-t-etched.step / a8653klptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a8653klptr-t.step / a8653klptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (37 pp, sha256 217c0a15c2d79b3e, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF