component
A8603KESTR-R
Public Made by Adomby adom
Allegro MicroSystems, LLC AC-DC Controllers & Regulators, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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A8603KESTR-R
Allegro MicroSystems, LLC · AC-DC Controllers & Regulators · QFN-24-EP(4x4)
A8603KESTR-R from Allegro MicroSystems, LLC, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input supply voltage for the IC, 3 to 10 V. |
| 2 | FAULT | output | Open-drain output that pulls low in case of an error condition. |
| 3 | EN | input | Enable pin for the IC; the system can only be enabled after VIN is above the UVLO level. |
| 4 | VCOM | power_out | Output from the internal low-dropout (LDO) regulator powered by AVDD, providing 3 to 7.5 V. |
| 5 | GNDVCOM | power_in | Ground reference for VCOM; connect to the ground plane. |
| 6 | NC | unconnected | No connect, reserved for test mode; connect to GND in the actual PCB. |
| 7 | SCL | input | I2C clock signal generated by the master. |
| 8 | SDA | bidirectional | I2C data signal, acting as an input or open-drain output depending on data direction. |
| 9 | ADDR | input | I2C address selection, giving up to 4 physical IC addresses based on voltage level. |
| 10 | FSET | input | Input for synchronizing the boost and charge-pump switching frequency to an external clock, or connection to an external resistor that sets the switching frequency (350 kHz to 2.25 MHz). |
| 11 | BIAS | power_out | Output from the internal 2.8 V bias regulator; decouple to GND with a 1 μF ceramic capacitor. |
| 12 | COMP | passive | Compensation pin for the external RZ and CZ components. |
| 13 | AVDD | power_out | Output from the internal LDO powered by VOUT. |
| 14 | AGND | power_in | Analog ground reference for signals; connect to the ground plane. |
| 15 | VGL | power_out | Inverted charge-pump output (negative supply, 4 to -12 V). |
| 16 | CP22 | passive | Capacitor terminal for the inverted charge pump. |
| 17 | CP21 | passive | Capacitor terminal for the inverted charge pump. |
| 18 | VGH | power_out | Output of the 2× charge pump (positive supply, 14 to 29 V). |
| 19 | VGH3 | power_out | Output of the 3× charge pump. |
| 20 | CP11 | passive | Capacitor terminal for the charge pump. |
| 21 | CP12 | passive | Capacitor terminal for the charge pump. |
| 22 | VOUT | power_in | Connect to the boost output to supply the internal LDO and charge-pump regulators. |
| 23 | PGND | power_in | Power ground for the internal boost switch; connect to the ground terminal of the output ceramic capacitor(s). |
| 24 | SW | output | Internal boost converter switch node; absolute maximum continuous voltage is -0.6 to 22 V. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | QFN-24-EP(4x4) |
| Category | Power Supply Chip |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Pin Voltage | VIN | -0.3 | 11 | V | All voltages measured with respect to GND | 3 | |
| SW Pin Voltage (continuous) | VSW | -0.6 | 22 | V | Continuous | 3 | |
| SW Pin Voltage (spikes) | VSW | -1 | 40 | V | Voltage spikes (pulse width < 100 ns) | 3 | |
| OUT Pin Voltage | VOUT | -0.3 | 22 | V | 3 | ||
| AVDD Pin Voltage | VAVDD | -0.3 | V | Upper limit: lower of 16 or VOUT + 0.3 V | 3 | ||
| CP11 Pin Voltage | VCP11 | -0.3 | 31 | V | Positive charge pump | 3 | |
| CP12 Pin Voltage | VCP12 | -0.3 | V | Upper limit: VCP11 + 0.3 V; positive charge pump | 3 | ||
| VGH and VGH3 Pin Voltage | VVGH, VVGH3 | -0.3 | 31 | V | Positive charge pump | 3 | |
| CP21 Pin Voltage | VCP21 | -0.3 | 14 | V | Negative charge pump | 3 | |
| CP22 and VGL Pin Voltage | VCP22, VVGL | -14 | 0.3 | V | Negative charge pump | 3 | |
| FAULT Pin Voltage | VFAULT | -0.3 | V | Upper limit: lower of 10 or VVIN + 0.3 V | 3 | ||
| BIAS, COMP, FSET Pin Voltage | VBIAS, VCOMP, VFSET | -0.3 | 3.3 | V | 3 | ||
| VCOM Pin Voltage | VVCOM | -0.3 | V | Upper limit: lower of 8.5 or VAVDD + 0.3 V | 3 | ||
| AGND, PGND and GNDVCOM Pin Voltage | VAGND, VPGND, VGNDVCOM | -0.3 | 0.3 | V | 3 | ||
| Logic Pins (EN, SCL, SDA, ADDR, NC) | -0.3 | 5.5 | V | 3 | |||
| Operating Ambient Temperature | TA | -40 | 125 | °C | K temperature range | 3 | |
| Maximum Junction Temperature | TJ(max) | 150 | °C | 3 | |||
| Storage Temperature | Tstg | -55 | 150 | °C | 3 | ||
| Input Voltage | VIN | 3 | 10 | V | • | 6 | |
| VIN Pin Undervoltage Lockout (UVLO) Threshold | VUVLO | 2.8 | 2.9 | V | VIN rising • | 6 | |
| Shutdown BIAS Current | IVINBIAS(SD) | 1 | 10 | µA | Current into VIN pin, EN = low • | 6 | |
| Switch Peak Current Limit | ISWILIM | 2.2 | 2.6 | 3 | A | Cycle-by-cycle current limit • | 6 |
| Switch On-Resistance | RDS(on) | 0.4 | 0.7 | Ω | ISW = 0.4 A | 6 | |
| Switch Minimum On-Time | tON(MIN) | 65 | 120 | ns | • | 6 | |
| Switch Minimum Off-Time | tOFF(MIN) | 60 | 100 | ns | • | 6 | |
| VOUT Pin Leakage Current | IOUT(LKG) | 25 | 37 | µA | VOUT = 10 V, EN = low | 6 | |
| SW Pin Overvoltage Protection Threshold | VSW(OVP) | 18.6 | 21 | 23 | V | Measured from SW to GND • | 6 |
| Switching Frequency | fSW | 1.8 | 2 | 2.2 | MHz | RFSET_SYNC = 5.1 kΩ • | 6 |
| Synchronization Frequency | fSYNC | 0.35 | 2.25 | MHz | External logic signal connected to FSET_SYNC pin • | 6 | |
| EN Pin Logic High | VIH_EN | 1.8 | V | • | 7 | ||
| EN Pin Logic Low | VIL_EN | 0.8 | V | • | 7 | ||
| FSET Pin Input Logic High | VIH_FSE | 1.5 | V | When used in external sync mode • | 7 | ||
| AVDD Output Voltage | VAVDD | 5 | 15 | V | • | 7 | |
| VCOM Output Voltage | VVCOM | 2.5 | 7.5 | V | VAVDD > VVCOM + 1.5 V • | 7 | |
| VGH Output Voltage | VVGH | 10 | 30 | V | VGH & VGH3 shorted • | 7 | |
| VGL Output Voltage | VVGL | -12 | -4 | V | • | 7 | |
| AVDD OCP Trip Level | IAVDD(OCP) | 200 | 275 | 350 | mA | Includes IVCOM | 8 |
| VCOM OCP Trip Level | IVCOM(OCP) | 36 | 45 | 54 | mA | 8 | |
| VGH OCP Trip Level | IVGH(OCP) | 11 | 20 | 26 | mA | 8 | |
| VGL OCP Trip Level | IVGL(OCP) | 11 | 20 | 26 | mA | Current into VGL pin | 8 |
| AVDD Load Regulation | VAVDDreg | -0.1 | 0.1 | V | VAVDD = 10 V, IAVDD = 10 to 100 mA • | 8 | |
| VGH Load Regulation | VVGHreg | -0.1 | 0.1 | V | VVGH = 20 V, IVGH = 0.4 to 4 mA • | 8 | |
| VGL Load Regulation | VVGLreg | -0.1 | 0.1 | V | VVGL = -8 V, IVGL = -0.8 to -8 mA • | 8 | |
| AVDD Accuracy | ErrAVDD | -2.1 | 2.1 | % | Reg00 = 0x40 (VAVDD = 10.04 V), IAVDD = 50 mA • | 8 | |
| VCOM Accuracy | ErrVCOM | -2.1 | 2.1 | % | Reg01,02 = 0x100 (VVCOM = 5.005 V), IVCOM = 10 mA • | 8 | |
| VGH Accuracy | errVGH | -2.5 | 2.5 | % | Reg04 = 0x40 (VVGH = 20.65 V), IVGH = 2 mA • | 8 | |
| VGL Accuracy | errVGL | -2.5 | 2.5 | % | Reg03 = 0x20 (VVGL = -8.39 V), IVGL = -4 mA • | 8 | |
| VCOM Temperature Coefficient | TCVCOM | -100 | 150 | µV/°C | VVCOM = 5 V, -30°C < TA < 85°C, ILOAD = 10 mA • | 8 | |
| Minimum Dropout for VCOM from AVDD | VVCOM(DO) | 1.5 | V | VAVDD = 7 V, IVCOM = 20 mA | 8 | ||
| FAULT Pull-Down Voltage | VFAULT(PD) | 0.4 | V | Fault condition asserted, pull-up current = 1 mA | 8 | ||
| Shutdown Timeout | tSD_TO | 40 | 50 | 65 | ms | All outputs discharged to below 10% target (30% for VGL and VGH) | 8 |
| Overcurrent Protection (OCP) Timeout | tOCP_TO | 40 | 50 | 60 | ms | Maximum time for any output to stay in OCP fault condition before shutdown. | 8 |
| TSD Threshold | TTSD | 155 | 165 | °C | Temperature rising | 9 | |
| Logic Input Low (SDA, SCL) | VSCL(L) | 0.8 | V | 9 | |||
| Logic Input High (SDA, SCL) | VSCL(H) | 2.3 | V | 9 | |||
| SCL Clock Frequency | fCLK | 400 | KHz | 9 | |||
| Data Setup Time | tSU:DAT | 100 | ns | 42 | |||
| Data Hold Time | tHD:DAT | 0 | 900 | ns | 42 | ||
| Output Fall Time from VSCL(H) to VSCL(L) | tOF | 250 | ns | 42 | |||
| Package Thermal Resistance | RθJA | 37 | °C/W | Package ES on 4-layer PCB based on JEDEC standard | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | ambient temperatures. It is lead (Pb) free with 100% matte-tin leadframe plating. | 1 |
CAD (KiCad official)
- Symbol:
A8603KESTR-R - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
a8603kestr-r-etched.step/a8603kestr-r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a8603kestr-r.step/a8603kestr-r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (42 pp, sha256
885e761285dfc7f9, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).