component
A8586KEJTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC DC-DC Converters, DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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A8586KEJTR-T
Allegro MicroSystems, LLC · DC-DC Converters · DFN-10-EP(3x3)
A8586KEJTR-T from Allegro MicroSystems, LLC, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | power_out | Source of the internal MOSFET; connect the output inductor (LO) and freewheel diode (D) cathode close to this pin with wide traces (pins 1 and 2 are both SW). |
| 2 | SW | power_out | Source of the internal MOSFET; connect the output inductor (LO) and freewheel diode (D) cathode close to this pin with wide traces (pins 1 and 2 are both SW). |
| 3 | EN | input | High-voltage enable input (rated 40 V); set high to turn the regulator on, low to turn it off, and it can be tied to VIN if no logic signal is available. |
| 4 | COMP | passive | Error amplifier output and compensation node for the current-mode control loop; connect a series RC network from this pin to GND. |
| 5 | FB | input | Feedback (negative) input to the error amplifier; connect a resistor divider from VOUT to this pin to program the output voltage (0.792 V typical reference). |
| 6 | GND | power_in | Ground connection. |
| 7 | FREQ | passive | Frequency setting pin; a resistor RFREQ from this pin to GND sets the PWM switching frequency (45 kΩ gives 2.0 MHz typical). |
| 8 | VIN | power_in | Power input for the control circuits and drain of the internal high-side N-channel MOSFET; connect to a 3.8 to 36 V supply with a ceramic capacitor placed very close to it (pins 8 and 9 are both VIN). |
| 9 | VIN | power_in | Power input for the control circuits and drain of the internal high-side N-channel MOSFET; connect to a 3.8 to 36 V supply with a ceramic capacitor placed very close to it (pins 8 and 9 are both VIN). |
| 10 | BST | passive | Bootstrap capacitor connection; connect a 100 nF capacitor from this pin to SW, and a series BOOT resistor is not recommended. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | DFN-10-EP(3x3) |
| Category | Power Management ICs |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Input Voltage | VIN | 3.8 | 12 | 36 | V | VEN ≥ 2.5 V | 5 |
| VIN UVLO Start | VIN(START) | 2.6 | 3 | 3.4 | V | VIN rising | 5 |
| Supply Quiescent Current | IQ | 27 | 36 | µA | No load, VFB = 0.9 V, A8586 only, -40°C ≤ TJ ≤ 65°C | 5 | |
| Sleep Quiescent Current | IQ(SLEEP) | 11 | 18 | µA | VEN = 0 V | 5 | |
| Switching Frequency | fSW | 1.6 | 2 | 2.4 | MHz | RFSET = 45 kΩ | 5 |
| Minimum On-Time | tON(MIN) | 80 | 160 | ns | 5 | ||
| MOSFET Leakage | IFET(LKG) | 0.1 | 1 | µA | VEN = 0 V, VIN = 12 V, VSW = 0 V, TJ = 25°C | 5 | |
| Feedback Voltage | VFB | 0.786 | 0.792 | 0.803 | V | 4.5 V ≤ VIN ≤ 36 V, TJ = 25°C | 5 |
| Feedback Voltage | VFB | 0.773 | 0.812 | V | 4.5 V ≤ VIN ≤ 36 V, -40°C ≤ TJ ≤ 125°C | 5 | |
| Error Amp Transconductance | gm | 35 | 60 | 95 | µA/V | ICOMP = ±3 µA | 5 |
| Current Limit | ILIM | 4 | 5.5 | A | 5 | ||
| Slope Compensation | SE(2MHz) | 2.2 | 3.1 | 4 | A/µs | Measured at fSW = 2 MHz | 5 |
| EN Threshold Rising | VEN(H) | 1.2 | 1.5 | 1.85 | V | VEN rising | 5 |
| EN Threshold Falling | VEN(L) | 1 | 1.2 | 1.4 | V | VEN falling | 5 |
| VIN UVLO Hysteresis | VIN(HYS) | 0.4 | V | 5 | |||
| Thermal Shutdown Threshold | TTSD | 170 | °C | TJ rising | 5 | ||
| Thermal Shutdown Hysteresis | THYS | 20 | °C | 5 | |||
| Minimum Off-Time | tOFF(MIN) | 100 | ns | 5 | |||
| MOSFET On Resistance | RDS(on) | 150 | mΩ | VBOOT-SW = 5 V | 5 | ||
| Error Amp Voltage Gain | AVOL | 1000 | V/V | 5 | |||
| Error Amp Min. Source Current | IEA(SOURCE) | -5 | µA | VFB = 0.7 V | 5 | ||
| Error Amp Min. Sink Current | IEA(SINK) | 5 | µA | VFB = 0.9 V | 5 | ||
| Low IQ Peak Current Threshold | IPEAK(LO_IQ) | 800 | mA | 5 | |||
| SS Ramp Time | tSS | 1.5 | ms | 0 V < VFB < 0.8 V | 5 | ||
| COMP to Current Sense Transductance | GCS | 9 | A/V | 5 | |||
| EN Hysteresis | VEN(HYS) | 300 | mV | 5 | |||
| Input Voltage (recommended) | VIN | 3.8 | 36 | V | 2 | ||
| Junction Temperature (recommended) | TJ | -40 | 150 | °C | 2 | ||
| Input Voltage | VIN | -0.3 | 40 | V | 2 | ||
| Switch Node Voltage | VSW | -0.3 | V | upper limit VIN + 0.3 V | 2 | ||
| Switch Node Voltage transient | VSW | -1.5 | V | t < 250 ns | 2 | ||
| Bootstrap Pin to Switch Node | VBST-SW | -0.3 | 6 | V | 2 | ||
| EN, FREQ pins | -0.3 | V | upper limit VIN + 0.3 V | 2 | |||
| All other pins | -0.3 | 6 | V | 2 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 2 | ||
| Storage Temperature Range | Tstg | -40 | 150 | °C | 2 | ||
| Junction-to-Ambient Thermal Resistance | RθJA | 45 | °C/W | DFN-10 (EJ) package on 4-layer PCB based on JEDEC standard | 2 |
CAD (KiCad official)
- Symbol:
A8586KEJTR-T - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
a8586kejtr-t-etched.step/a8586kejtr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a8586kejtr-t.step/a8586kejtr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (20 pp, sha256
fde98db0c4328c8c, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# A8586KEJTR-T
**Allegro MicroSystems, LLC** · DC-DC Converters · DFN-10-EP(3x3)
A8586KEJTR-T from Allegro MicroSystems, LLC, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | power_out | Source of the internal MOSFET; connect the output inductor (LO) and freewheel diode (D) cathode close to this pin with wide traces (pins 1 and 2 are both SW). |
| 2 | SW | power_out | Source of the internal MOSFET; connect the output inductor (LO) and freewheel diode (D) cathode close to this pin with wide traces (pins 1 and 2 are both SW). |
| 3 | EN | input | High-voltage enable input (rated 40 V); set high to turn the regulator on, low to turn it off, and it can be tied to VIN if no logic signal is available. |
| 4 | COMP | passive | Error amplifier output and compensation node for the current-mode control loop; connect a series RC network from this pin to GND. |
| 5 | FB | input | Feedback (negative) input to the error amplifier; connect a resistor divider from VOUT to this pin to program the output voltage (0.792 V typical reference). |
| 6 | GND | power_in | Ground connection. |
| 7 | FREQ | passive | Frequency setting pin; a resistor RFREQ from this pin to GND sets the PWM switching frequency (45 kΩ gives 2.0 MHz typical). |
| 8 | VIN | power_in | Power input for the control circuits and drain of the internal high-side N-channel MOSFET; connect to a 3.8 to 36 V supply with a ceramic capacitor placed very close to it (pins 8 and 9 are both VIN). |
| 9 | VIN | power_in | Power input for the control circuits and drain of the internal high-side N-channel MOSFET; connect to a 3.8 to 36 V supply with a ceramic capacitor placed very close to it (pins 8 and 9 are both VIN). |
| 10 | BST | passive | Bootstrap capacitor connection; connect a 100 nF capacitor from this pin to SW, and a series BOOT resistor is not recommended. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | DFN-10-EP(3x3) |
| Category | Power Management ICs |
| Pins | 11 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Input Voltage | VIN | 3.8 | 12 | 36 | V | VEN ≥ 2.5 V | 5 |
| VIN UVLO Start | VIN(START) | 2.6 | 3 | 3.4 | V | VIN rising | 5 |
| Supply Quiescent Current | IQ | | 27 | 36 | µA | No load, VFB = 0.9 V, A8586 only, -40°C ≤ TJ ≤ 65°C | 5 |
| Sleep Quiescent Current | IQ(SLEEP) | | 11 | 18 | µA | VEN = 0 V | 5 |
| Switching Frequency | fSW | 1.6 | 2 | 2.4 | MHz | RFSET = 45 kΩ | 5 |
| Minimum On-Time | tON(MIN) | | 80 | 160 | ns | | 5 |
| MOSFET Leakage | IFET(LKG) | | 0.1 | 1 | µA | VEN = 0 V, VIN = 12 V, VSW = 0 V, TJ = 25°C | 5 |
| Feedback Voltage | VFB | 0.786 | 0.792 | 0.803 | V | 4.5 V ≤ VIN ≤ 36 V, TJ = 25°C | 5 |
| Feedback Voltage | VFB | 0.773 | | 0.812 | V | 4.5 V ≤ VIN ≤ 36 V, -40°C ≤ TJ ≤ 125°C | 5 |
| Error Amp Transconductance | gm | 35 | 60 | 95 | µA/V | ICOMP = ±3 µA | 5 |
| Current Limit | ILIM | 4 | 5.5 | | A | | 5 |
| Slope Compensation | SE(2MHz) | 2.2 | 3.1 | 4 | A/µs | Measured at fSW = 2 MHz | 5 |
| EN Threshold Rising | VEN(H) | 1.2 | 1.5 | 1.85 | V | VEN rising | 5 |
| EN Threshold Falling | VEN(L) | 1 | 1.2 | 1.4 | V | VEN falling | 5 |
| VIN UVLO Hysteresis | VIN(HYS) | | 0.4 | | V | | 5 |
| Thermal Shutdown Threshold | TTSD | | 170 | | °C | TJ rising | 5 |
| Thermal Shutdown Hysteresis | THYS | | 20 | | °C | | 5 |
| Minimum Off-Time | tOFF(MIN) | | 100 | | ns | | 5 |
| MOSFET On Resistance | RDS(on) | | 150 | | mΩ | VBOOT-SW = 5 V | 5 |
| Error Amp Voltage Gain | AVOL | | 1000 | | V/V | | 5 |
| Error Amp Min. Source Current | IEA(SOURCE) | | -5 | | µA | VFB = 0.7 V | 5 |
| Error Amp Min. Sink Current | IEA(SINK) | | 5 | | µA | VFB = 0.9 V | 5 |
| Low IQ Peak Current Threshold | IPEAK(LO_IQ) | | 800 | | mA | | 5 |
| SS Ramp Time | tSS | | 1.5 | | ms | 0 V < VFB < 0.8 V | 5 |
| COMP to Current Sense Transductance | GCS | | 9 | | A/V | | 5 |
| EN Hysteresis | VEN(HYS) | | 300 | | mV | | 5 |
| Input Voltage (recommended) | VIN | 3.8 | | 36 | V | | 2 |
| Junction Temperature (recommended) | TJ | -40 | | 150 | °C | | 2 |
| Input Voltage | VIN | -0.3 | | 40 | V | | 2 |
| Switch Node Voltage | VSW | -0.3 | | | V | upper limit VIN + 0.3 V | 2 |
| Switch Node Voltage transient | VSW | -1.5 | | | V | t < 250 ns | 2 |
| Bootstrap Pin to Switch Node | VBST-SW | -0.3 | | 6 | V | | 2 |
| EN, FREQ pins | | -0.3 | | | V | upper limit VIN + 0.3 V | 2 |
| All other pins | | -0.3 | | 6 | V | | 2 |
| Junction Temperature | TJ | -40 | | 150 | °C | | 2 |
| Storage Temperature Range | Tstg | -40 | | 150 | °C | | 2 |
| Junction-to-Ambient Thermal Resistance | RθJA | | 45 | | °C/W | DFN-10 (EJ) package on 4-layer PCB based on JEDEC standard | 2 |
## CAD (KiCad official)
- Symbol: `A8586KEJTR-T`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`
- 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `a8586kejtr-t-etched.step` / `a8586kejtr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a8586kejtr-t.step` / `a8586kejtr-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a8586kejtr-t-datasheet.pdf) (20 pp, sha256 `fde98db0c4328c8c`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/a8586kejtr-t-datasheet.pdf)