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A8522KLPTR-T

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Allegro MicroSystems, LLC LED Drivers, TSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdisplay modules - led drivers - display driversa8522klptr-tfactory-2.0.0extractor-text

Verified A8522KLPTR-T

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier lcsc, 29 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: A8522KLPTR-T · TSSOP-28-EP · 29 pins
  • ✓copper: 29 copper pads, none touching another net
  • ✓datasheet: all 29 pin names found in the 65-page datasheet
  • ✓distributor: lcsc C2679119, digikey A8522KLPTR-T-ND, mouser 250-A8522KLPTR-T
  • ✓family: TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-4h7n3371/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 29 pins = 29 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 29 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ a8522klptr-t.kicad_sym✓ a8522klptr-t.kicad_mod✓ a8522klptr-t.step
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Ray Publish 0.1.0 e5652ac 19h ago

A8522KLPTR-T

Allegro MicroSystems, LLC · LED Drivers · TSSOP-28-EP

A8522KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GATE output Gate driver for an optional external PMOS input-disconnect switch, pulled high to turn off the input supply on a fault such as output shorted to GND; left open if not used.
2 INS input Input current sense used together with VIN to detect input overcurrent faults; tie to VIN if not used.
3 VIN power_in Input power to the A8522, specified over an input voltage range of 4.5 to 36 V.
4 EN input Enable input that keeps the IC in shutdown while EN = VEN(L) and enables the part when connected to VEN(H) or to VIN.
5 FSET/SYNC bidirectional A resistor RFSET from this pin to GND sets the switching frequency, and the pin can also be used to synchronize to an external switching frequency.
6 COMP passive Output of the error amplifier and compensation node; connect a type-2 feedback network from this pin to AGND for loop compensation.
7 AGND power_in Analog ground for noise-sensitive components, especially COMP, and connected to the thermal pad.
8 VDD power_out Output of the internal LDO; connect a 0.47 µF decoupling capacitor between this pin and AGND.
9 FLAG output Active-low open-drain pin indicating that system attention is required, such as during startup or a fault; connect a 10 to 100 kΩ pull-up to the target logic level.
10 LED1 passive LED current sink channel 1, up to 60 mA; any unused LEDx pin should be connected to GND through a 4.7 kΩ resistor.
11 LED2 passive LED current sink channel 2, up to 60 mA; any unused LEDx pin should be connected to GND through a 4.7 kΩ resistor.
12 LED3 passive LED current sink channel 3, up to 60 mA; any unused LEDx pin should be connected to GND through a 4.7 kΩ resistor.
13 LED4 passive LED current sink channel 4, up to 60 mA; any unused LEDx pin should be connected to GND through a 4.7 kΩ resistor.
14 LED5 passive LED current sink channel 5, up to 60 mA; any unused LEDx pin should be connected to GND through a 4.7 kΩ resistor.
15 AGND power_in Analog ground for noise-sensitive components, especially COMP, and connected to the thermal pad.
16 LED6 passive LED current sink channel 6, up to 60 mA; any unused LEDx pin should be connected to GND through a 4.7 kΩ resistor.
17 LED7 passive LED current sink channel 7, up to 60 mA; any unused LEDx pin should be connected to GND through a 4.7 kΩ resistor.
18 LED8 passive LED current sink channel 8, up to 60 mA; any unused LEDx pin should be connected to GND through a 4.7 kΩ resistor.
19 NC unconnected No connect; terminate to GND through a 4.7 kΩ resistor and do not short directly to GND.
20 NC unconnected No connect; terminate to GND through a 4.7 kΩ resistor and do not short directly to GND.
21 GPO2 output General purpose open-drain output 2, programmable by internal register.
22 GPO1 output General purpose open-drain output 1, programmable by internal register.
23 SDA bidirectional I2C data signal.
24 SCL input I2C clock signal.
25 ADDR input Four-level input that sets up to 4 physical IC addresses based on the voltage level set by a resistor to GND.
26 PGND power_in Power ground for the internal NMOS switching device; connect to the output capacitor ground and to the thermal pad.
27 OVP input Connect to output voltage VOUT to provide output overvoltage protection (OVP) and undervoltage protection (UVP).
28 SW passive Drain of the internal NMOS switch of the boost converter.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package TSSOP-28-EP
Category Display Modules / LED Drivers / Display Drivers
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
LEDx Pins VLEDx -0.3 42 V 3
FLAG, GPO2, and OVP Pins -0.3 42 V 3
EN, VIN, INS, and GATE Pins -0.3 40 V INS and GATE pins should not exceed VIN by more than 0.4 V 3
SW Pin, continuous VSW -0.6 42 V Continuous 3
SW Pin, transient VSW -1 46 V t < 50 ns 3
VDD, FSET/SYNC, COMP, GPO1, SDA, SCL, and ADDR Pins -0.3 5.5 V 3
Operating Ambient Temperature TA -40 125 °C K temperature range 3
Maximum Junction Temperature TJ(max) 150 °C 3
Storage Temperature Tstg -65 150 °C 3
Package Thermal Resistance RθJA 28 °C/W On 4-layer PCB based on JEDEC standard 3
Input Voltage Range VIN 4.5 36 V Measured at the VIN pin 6
VIN Pin UVLO Start VINUV(ON) 4.35 V VIN rising 6
VIN Pin UVLO Stop VINUV(OFF) 3.9 V VIN falling 6
Input Sleep Supply Current IQSLEEP 3.5 10 µA Sum of VIN and INS pin currents, VIN = VINS = 16 V, VEN = 0 V 6
EN Input Logic Level - Low VEN(L) 0.4 V 4.5 V < VIN < 36 V 6
EN Input Logic Level - High VEN(H) 1.5 V 4.5 V < VIN < 36 V 6
Overvoltage Threshold (minimum setting) VOVPMIN 7.5 8 8.5 V OVP register = xxx0 0000 6
Overvoltage Threshold (maximum setting) VOVPMAX 38 39 40 V OVP register = xxx1 1111 6
OVP Leakage Current IOVPLKG 0.1 1 µA VOVP =16 V, EN = VEN(L) 6
Switch On-Resistance RDS(ON) 220 350 mΩ ISW = 0.750 A, VIN = 16 V 6
Switch Leakage Current ISWLKG 0.1 10 µA VSW = 16 V, EN = VEN(L), TA = TJ = -40°C to 85°C 6
Cycle-by-Cycle Switch Current Limit ISW(LIM) 3.6 4.2 4.8 A 6
Secondary Switch Current Limit ISWLIM(sec) 5.6 7 A Higher than maximum ISW(LIM) at any condition (A8522 latches when detected) 6
Minimum Switch On-Time tSWONTIME 85 120 ns RFSET = 10 kΩ 6
Minimum Switch Off-Time tSWOFFTIME 55 85 ns RFSET = 10 kΩ 6
Boost Stage Switching Frequency fSW 1.8 2 2.2 MHz RFSET = 10 kΩ 7
Synchronized Boost Stage Switching Frequency fSW_SYNC 400 2300 kHz 7
Synchronization Input Minimum Off-Time tSYNCPWOFF 150 ns 7
Synchronization Input Minimum On-Time tSYNCPWON 150 ns 7
Synchronization Input Logic, Low VSYNCON(L) 0.4 V 7
Synchronization Input Logic, High VSYNCON(H) 2 V 7
LEDx Accuracy (Average) ErrLEDx 0.7 3 % Measured at ILEDMAX (maximum LED current) 7
LEDx Matching ΔILEDx 0.8 3 % Compared to average ILEDx, measured at ILEDMAX 7
LEDx Regulation Voltage VREG 0.85 1 V ISET register= xx11 1111 7
ILEDx Step Size ISETSTEP 0.9 1 1.1 mA Total 64 steps 7
Maximum LEDx Current (Average) ILEDMAX 62 64 66 mA ISET register = xx11 1111 7
Interrupt Pin Pull-Down Voltage 0.4 V Fault/Interrupt condition asserted, pull-up current = 0.5 mA 7
Interrupt Pin Leakage Current 1 µA Fault/Interrupt condition cleared, pull-up to 3.6 V 7
Master Clock Period TCLK 120 150 180 ns 7
Master Clock Temperature Deviation DTCLK -2.5 2.5 % TCLK change over temperature range 7
GATE Voltage at On VGSON 5 8 V Gate-to-source voltage when gate is on, measured as VIN, VGATE 8
GATE Pin Leakage Current IGLKG 1 µA EN = VEN(L), VGATE = VIN 8
INS Trip Point VINSTRIP 90 105 120 mV Measured between VIN and INS 8
Thermal Shutdown Threshold TSD 155 170 °C Temperature rising 8
Logic Input (SDA, SCL), Low VSCL(L) 0.8 V 8
Logic Input (SDA, SCL), High VSCL(H) 2.3 V 8
Logic Input Current II2CI -1 1 µA 8
Output Voltage SDA VI2COut(L) 0.4 V SDA = low, pull-up current = 2.5 mA 8
Output Leakage SDA II2CLKG 1 µA EN = low, pull-up to 5.5 V 8
SCL Clock Frequency fCLK 400 kHz 8
Voltage Level for Address 100,0000 VADDLEVEL1 0 0.5 V ADDR connected to GND 8
Voltage Level for Address 101,0000 VADDLEVEL2 0.9 1.3 V RADDR = 110 kΩ from ADDR to GND 8
Voltage Level for Address 110,0000 VADDLEVEL3 1.75 2.45 V RADDR = 210 kΩ from ADDR to GND 8
Voltage Level for Address 111,0000 VADDLEVEL4 3.2 3.6 V ADDR connected to VDD pin or open 8
ADDR Pull-Up Current IADDR -8.5 -10 -11.5 µA VADDR = 1 V 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin A8522KLPTR-T -40 to 125 28-pin TSSOP with exposed thermal pad 4000 pieces per 13-in. reel 100% matte tin 2

CAD (KiCad official)

  • Symbol: A8522KLPTR-T
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: TSSOP-28-EP (KiCad packages3D, STEP)
  • 3D model files: a8522klptr-t-etched.step / a8522klptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a8522klptr-t.step / a8522klptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (65 pp, sha256 d6a7732d3abb26ac, retrieved 2026-11-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF