component
A8519KLPTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC LED Drivers, TSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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A8519KLPTR-T
Allegro MicroSystems, LLC · LED Drivers · TSSOP-20-EP
A8519KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | passive | Output of the error amplifier and compensation node; connect an Rz-Cz-Cp network from this pin to GND for control loop compensation. |
| 2 | PGND | power_in | Power ground for the internal N-channel MOSFET switching device; connect to the PCB ground plane. |
| 3 | OVP | input | Overvoltage protection input; connect an external resistor from VOUT to this pin to set the overvoltage protection level (OVP pin threshold 7 V to 9.5 V). |
| 4 | VOUT | input | Connect directly to the boost output voltage; maximum output voltage is 40 V. |
| 5 | SW | passive | Drain of the internal N-channel MOSFET switch of the boost converter; the SW pin is rated -0.6 V to 42 V continuous. |
| 6 | GATE | output | Gate driver output for control of an external P-channel MOSFET input disconnect switch. |
| 7 | VSENSE | input | Connect to the negative side of the current sense resistor RSC; the threshold is measured as VIN minus VSENSE, with a fixed current sink for trip threshold adjustment. |
| 8 | VIN | power_in | Input power to the IC and the positive input for the current sense resistor; the input voltage range is 4.5 V to 40 V. |
| 9 | FAULT | output | Open-drain fault output that is pulled low when a fault occurs; connect a 100 kΩ resistor between this pin and the desired logic level voltage. |
| 10 | CLKOUT | output | Logic output representing the internal boost oscillator switching frequency, allowing other converters to be synchronized to it. |
| 11 | VDD | power_out | Output of the internal LDO bias regulator; connect a 1 µF decoupling capacitor between this pin and GND. |
| 12 | APWM | input | Analog trimming or dimming input; applying a digital PWM signal to this pin adjusts the internal IISET current. |
| 13 | PWM | input | Enables the IC when pulled high and controls LED intensity by pulse-width modulation; typical PWM dimming frequency is 100 Hz to 400 Hz. |
| 14 | FSET | input | Frequency and synchronization pin; a resistor RFSET from this pin to GND sets the switching frequency, or an external clock from 320 kHz to 2.3 MHz synchronizes it with dithering disabled. |
| 15 | ISET | input | Connect the RISET resistor between this pin and GND to set the desired LED current. |
| 16 | AGND | power_in | LED current ground; connect to the PCB ground plane. |
| 17 | LED1 | input | LED current sink #1; connect the cathode of the LED string to this pin, and terminate it to GND through 3.09 kΩ if unused. |
| 18 | LED2 | input | LED current sink #2; connect the cathode of the LED string to this pin, and terminate it to GND through 3.09 kΩ if unused. |
| 19 | LED3 | input | LED current sink #3; connect the cathode of the LED string to this pin, and terminate it to GND through 3.09 kΩ if unused. |
| 20 | LED4 | input | LED current sink #4; connect the cathode of the LED string to this pin, and terminate it to GND through 3.09 kΩ if unused. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | TSSOP-20-EP |
| Category | Nixie Tube Driver/LED Driver |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| LEDx Pins voltage | VLEDx | -0.3 | 40 | V | x = 1, 2, 3, or 4 | 2 | |
| OVP Pin voltage | VOVP | -0.3 | 40 | V | 2 | ||
| VIN, VOUT Pins voltage | VIN, VOUT | -0.3 | 40 | V | 2 | ||
| VSENSE, GATE Pins voltage | VSENSE, VGATE | -7.4 | 0.4 | V | Relative to VIN (VIN -7.4 to VIN +0.4) | 2 | |
| SW Pin voltage continuous | VSW | -0.6 | 42 | V | Continuous | 2 | |
| SW Pin voltage transient | VSW | -1 | 48 | V | t < 50 ns | 2 | |
| FAULT Pin voltage | VFAULT | -0.3 | 40 | V | 2 | ||
| APWM, PWM, CLKOUT, COMP, FSET, ISET, VDD Pins voltage | -0.3 | 5.5 | V | 2 | |||
| Operating Ambient Temperature | TA | -40 | 125 | °C | K temperature range | 2 | |
| Maximum Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature | Tstg | -55 | 150 | °C | 2 | ||
| Input Voltage Range | VIN | 4.5 | 40 | V | ● guaranteed over full operating temperature range | 6 | |
| UVLO Start Threshold | VUVLOrise | 4.35 | V | VIN rising | 6 | ||
| UVLO Stop Threshold | VUVLOfall | 3.9 | V | VIN falling | 6 | ||
| UVLO Hysteresis | VUVLOHYS | 300 | 450 | 600 | mV | 6 | |
| Input Quiescent Current | IQ | 8 | 15 | mA | VPWM = VIH, fSW = 2 MHz | 6 | |
| Input Sleep Supply Current | ISLEEP | 2 | 10 | µA | VIN = 16 V, VPWM = VSYNC = 0 V | 6 | |
| Input Logic Level Low | VIL | 0.4 | V | 6 | |||
| Input Logic Level High | VIH | 1.5 | V | 6 | |||
| PWM Input Pull-Down Resistor | REN | 60 | 100 | 140 | kΩ | VPWM = 5 V | 6 |
| APWM Input Pull-Down Resistor | RAPWM | 60 | 100 | 140 | kΩ | VPWM = VIH | 6 |
| APWM Frequency | fAPWM | 40 | 1000 | kHz | 6 | ||
| Output Logic Level Low | VOL | 0.3 | V | 5 V < VIN < 40 V | 6 | ||
| Output Logic Level High | VOH | 1.8 | V | 5 V < VIN < 40 V | 6 | ||
| OVP Pin Voltage Threshold | VOVP(th) | 7 | 8.3 | 9.5 | V | OVP pin connected to VOUT | 6 |
| OVP Pin Sense Current Threshold | IOVP(th) | 190 | 200 | 210 | µA | Current into OVP pin | 6 |
| OVP Pin Leakage Current | IOVP(LKG) | 0.1 | 1 | µA | VIN = 16 V, PWM = L | 6 | |
| OVP Accuracy | 5 | % | 6 | ||||
| Undervoltage Protection Threshold | VUVP(th) | 0.55 | 0.7 | V | Measured at VOUT pin when ROVP = 0 | 6 | |
| Secondary Overvoltage Protection | VOVP(sec) | 42 | 45 | 48 | V | Measured at SW pin | 6 |
| Switch On-Resistance | RSW | 100 | 250 | 500 | mΩ | ISW = 0.75 A, VIN = 16 V | 7 |
| Switch Leakage Current | ISW(LKG) | 0.1 | 1 | µA | VSW = 16 V, VPWM = VIL | 7 | |
| Switch Current Limit | ISW(LIM) | 3 | 3.65 | 4.5 | A | 7 | |
| Minimum Switch On-Time | tSW(on) | 45 | 65 | 85 | ns | 7 | |
| Minimum Switch Off-Time | tSW(off) | 65 | 85 | ns | 7 | ||
| Oscillator Frequency | fSW | 1.95 | 2.15 | 2.35 | MHz | RFSET = 10 kΩ | 7 |
| Oscillator Frequency | fSW | 0.9 | 1 | 1.1 | MHz | RFSET = 21.5 kΩ | 7 |
| Oscillator Frequency Dithering Range | fSW_DITH | -5 | 5 | % | RFSET = 10 kΩ | 7 | |
| Sync Input Logic Level Low | VSYNCL | 0.4 | V | FSET pin logic Low | 7 | ||
| Sync Input Logic Level High | VSYNCH | 2 | V | FSET pin logic High | 7 | ||
| Synchronized Switching Frequency | fSW(sync) | 320 | 2300 | kHz | 7 | ||
| Synchronization Input Min. Off-Time | tSYNC(off) | 150 | ns | 7 | |||
| Synchronization Input Min. On-Time | tSYNC(on) | 150 | ns | 7 | |||
| LEDx Accuracy | ErrLED | 0.7 | 3 | % | RISET = 8.33 kΩ | 7 | |
| LEDx Matching | ΔLEDx | 0.8 | 2 | % | IISET = 120 µA | 7 | |
| LEDx Regulation Voltage | VLEDx | 750 | 850 | 975 | mV | VLED1 = VLED2 = VLED3 = VLED4, IISET = 120 µA | 7 |
| ISET to ILEDx Current Gain | AISET | 696 | 710 | 727 | A/A | IISET = 120 µA | 7 |
| ISET Pin Voltage | VISET | 0.987 | 1.017 | 1.047 | V | 7 | |
| Allowable ISET Current | IISET | 20 | 144 | µA | 7 | ||
| VLEDx Short Detect | VLEDx(SC) | 4.7 | 5.2 | 7 | V | While LED sinks are in regulation; sensed from VLEDx to AGND | 7 |
| Maximum PWM Dimming Until Off-Time | tPWML | 32750 | fSW cycles | 8 | |||
| Minimum PWM On-Time, first cycle | tPWMH(min1) | 0.75 | 2 | µs | First cycle when powering up IC (VPWM = 0 to 3.3 V) | 8 | |
| Minimum PWM On-Time, subsequent pulses | tPWMH(min) | 0.5 | 1 | µs | Subsequent PWM pulses | 8 | |
| PWM High to LED On Delay | td(PWMon) | 0.2 | 0.5 | µs | VPWM = 0 to 3.3 V | 8 | |
| PWM Low to LED Off Delay | td(PWMoff) | 0.36 | 0.5 | µs | VPWM = 3.3 to 0 V | 8 | |
| FAULT Pull-Down Voltage | VFAULT | 0.5 | V | IFAULT = 1 mA | 8 | ||
| Gate Shutdown Delay When Overcurrent Fault Is Tripped | tFAULT | 3 | µs | VIN, VSENSE = 200 mV, monitored at FAULT pin | 8 | ||
| VSENSE Trip Point | VSENSE(trip) | 95 | 110 | 125 | mV | Measured between VIN and VSENSE, Radj = 0 | 8 |
| VSENSE Pin Sink Current | IVSENSE | 17.2 | 21.5 | 25.8 | µA | 8 | |
| Package Thermal Resistance, LP on 2-layer 3 in2 PCB | RθJA | 40 | °C/W | LP Package on 2-layer 3 in2 PCB | 3 | ||
| Package Thermal Resistance, LP on 4-layer PCB | RθJA | 29 | °C/W | LP Package on 4-layer PCB, based on JEDEC Standards | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | A8519KLPTR-T -40 to 125 350 mV 20-pin TSSOP with exposed thermal pad 4000 pieces per reel 100% matte tin A8519KETTR-R -40 to 125 350 mV 28-pin 5 × 5 mm QFN with exposed thermal pad and sidewall plate | 2 |
CAD (KiCad official)
- Symbol:
A8519KLPTR-T - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: TSSOP-20-EP (KiCad packages3D, STEP)
- 3D model files:
a8519klptr-t-etched.step/a8519klptr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a8519klptr-t.step/a8519klptr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (38 pp, sha256
f15a7280a8b54665, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).