component
A8498SLJTR-T
Public Made by Adomby adom
Allegro MicroSystems LLC DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownA8498SLJTR-T
Allegro MicroSystems LLC · DC-DC Converters · SOIC-8-EP
A8498SLJTR-T from Allegro MicroSystems LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Gate drive boost node for the high-side switch drive, with a 0.01 µF ceramic CBOOT used in the reference designs. |
| 2 | ENB | input | On/off control logic input: pulling it to ground enables the device, an open circuit disables it, VENB(0) LOW level is 1.0 V max, and the absolute maximum input voltage is 7 V. |
| 3 | TSET | passive | Off-time setting pin: a resistor from this pin to ground sets the fixed off-time (for example, 63.4 kΩ gives tOFF for a 3.3 V output at 42 V input in the reference design). |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | FB | input | Feedback input for the adjustable regulator, regulated to a 0.8 V reference (0.784 to 0.816 V), with output adjustable from 0.8 to 24 V; the regulator invokes current limit when FB falls below 0.4 V. |
| 6 | VBIAS | power_in | Bias supply input, which should be connected to VOUT when the output target is between 3.3 and 5 V; absolute maximum rating is -0.3 to 7 V. |
| 7 | LX | output | Buck switching node, with a switching voltage minimum of -1 V in the absolute maximum ratings. |
| 8 | VIN | power_in | Supply input, rated for 8 to 50 V operation with an absolute maximum load supply voltage of 50 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage, VIN pin | VIN | 50 | V | 2 | |||
| Input Voltage, VBIAS pin | VBIAS | -0.3 | 7 | V | 2 | ||
| Switching Voltage | VS | -1 | V | 2 | |||
| Input Voltage Range, ENB pin | VENB | -0.3 | 7 | V | 2 | ||
| Operating Ambient Temperature Range | TA | -20 | 85 | °C | 2 | ||
| Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature | TS | -55 | 150 | °C | 2 | ||
| Package thermal resistance, junction to ambient (LJ) | RθJA | 35 | °C/W | 4-layer PCB | 2 | ||
| Input voltage range for electrical characteristics | VIN | 8 | 50 | V | Electrical characteristics test range, unless noted otherwise | 4 | |
| Junction temperature range for specifications | TJ | 0 | 125 | °C | Specifications assured by design and characterization | 4 | |
| VIN Quiescent Current | IVIN(Q) | 0.9 | 1.35 | mA | VENB = LOW, VIN = 42 V, VBIAS = 3.2 V, VFB = 1.5 V (not switching) | 4 | |
| VIN Quiescent Current | IVIN(Q) | 4.4 | 6.35 | mA | VENB = LOW, VIN = 42 V, VBIAS < 3 V, VFB = 1.5 V | 4 | |
| VIN Quiescent Current | IVIN(Q) | 100 | µA | VENB = HIGH | 4 | ||
| VBIAS Input Current | IBIAS | 3.5 | 5 | mA | VBIAS = VOUT | 4 | |
| Buck Switch On Resistance | RDS(on) | 450 | mΩ | TA = 25°C, IOUT = 3 A | 4 | ||
| Buck Switch On Resistance | RDS(on) | 650 | mΩ | TA = 125°C, IOUT = 3 A | 4 | ||
| Fixed Off-Time Proportion | -15 | 15 | % | Based on calculated value | 4 | ||
| Feedback Voltage | VFB | 0.784 | 0.8 | 0.816 | V | 4 | |
| Internal reference tolerance | -2 | 2 | % | Internal 0.8 V reference (stated in Functional Description text) | 5 | ||
| Output Voltage Regulation | VOUT | -3 | 3 | % | IOUT = 0 mA to 3 A | 4 | |
| Feedback Input Bias Current | IFB | -400 | -100 | 100 | nA | 4 | |
| Soft Start Time | tss | 5 | 10 | 15 | ms | 4 | |
| Buck Switch Current Limit | ICL | 3.5 | 5 | A | VFB > 0.4 V | 4 | |
| Buck Switch Current Limit | ICL | 0.5 | 1.5 | A | VFB < 0.4 V | 4 | |
| ENB Open Circuit Voltage | VOC | 2 | 7 | V | Output disabled | 4 | |
| ENB Input Voltage Threshold | VENB(0) | 1 | V | LOW level input (Logic 0), output enabled | 4 | ||
| ENB Input Current | IENB(0) | -10 | -1 | µA | VENB = 0 V | 4 | |
| VIN Undervoltage Threshold | VUVLO | 6.6 | 6.9 | 7.2 | V | VIN rising | 4 |
| VIN Undervoltage Hysteresis | VUVLO(hys) | 0.7 | 1.1 | V | VIN falling | 4 | |
| Thermal Shutdown Temperature | TJTSD | 165 | °C | Temperature increasing | 4 | ||
| Thermal Shutdown Hysteresis | TJTSD(hys) | 15 | °C | Recovery = TJTSD, TJTSD(hys) | 4 |
CAD (KiCad official)
- Symbol:
A8498SLJTR-T - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
a8498sljtr-t-etched.step/a8498sljtr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a8498sljtr-t.step/a8498sljtr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (10 pp, sha256
57fe234fb85add6d, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).