component
A8450KLBTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC AC-DC Controllers & Regulators, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
A8450KLBTR-T
Allegro MicroSystems, LLC · AC-DC Controllers & Regulators · SOIC-24-300mil
A8450KLBTR-T from Allegro MicroSystems, LLC, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBB | power_in | Load supply input; the electrical characteristics specify operation from 6 to 45 V with an absolute maximum rating of -40 V. |
| 2 | CP2 | passive | Charge pump capacitor positive side, connected to CP1 through a 0.1 µF ceramic capacitor (C8). |
| 3 | CP1 | passive | Charge pump capacitor negative side, connected to CP2 through a 0.1 µF ceramic capacitor (C8). |
| 4 | VCP | power_out | Charge pump output driving the N-channel buck switch; a 0.1 µF ceramic capacitor (C7) connects between VCP and VBB. |
| 5 | VREG11 | passive | Internal reference pin; the datasheet specifies no external connection for it. |
| 6 | GND | power_in | Power ground; internally fused ground lead for enhanced thermal dissipation. |
| 7 | GND | power_in | Power ground; internally fused ground lead for enhanced thermal dissipation. |
| 8 | ENB | input | Logic-level enable input; HIGH input level 2.7 to 6.5 V, LOW input level -0.3 to 0.8 V. |
| 9 | CPOR | passive | POR delay adjustment pin; external capacitor C9 sets tPOR using tPOR = 2.13×105 × CCPOR (ms, µF). |
| 10 | CLADJ | passive | Current limit pin for the adjustable regulator; it should be shorted to VREG if current limiting is not needed. |
| 11 | VADJBD | output | Base drive output for the adjustable regulator pass transistor, with base drive current of 5.0 to 16.0 mA. |
| 12 | FB | input | Feedback input for the adjustable regulator; feedback voltage VFB is 1.16 to 1.24 V. |
| 13 | V5A | power_out | 5 V analog regulator output of 200 mA, protected against short to supply; output voltage 4.9 to 5.1 V. |
| 14 | NPOR | output | Open-drain power-on-reset output that signals a POR event, with output voltage at most 400 mV when asserted. |
| 15 | NFAULT | output | Open-drain diagnostic output, pulled low during fault conditions. |
| 16 | V5D | power_out | 5 V digital regulator output of 200 mA; output voltage 4.9 to 5.1 V. |
| 17 | VREG | power_out | DC-to-DC converter output that supplies the linear regulators; regulated output voltage is 5.50 to 5.80 V. |
| 18 | GND | power_in | Power ground; internally fused ground lead for enhanced thermal dissipation. |
| 19 | GND | power_in | Power ground; internally fused ground lead for enhanced thermal dissipation. |
| 20 | CL33 | passive | Current limit pin for the 3.3 V regulator, set by resistor R3; it should be shorted to VREG if current limiting is not needed. |
| 21 | V33BD | output | Base drive output for the 3.3 V regulator pass transistor. |
| 22 | V33 | power_out | 3.3 V linear regulator output; output voltage 3.234 to 3.366 V. |
| 23 | ENBAT | input | High-voltage enable input; HIGH input level 2.7 to 45 V, LOW input level -0.3 to 0.8 V. |
| 24 | LX | output | Buck converter switching regulator output; LX voltage is rated -2 V to VBB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-24-300mil |
| Category | Power Supply Chip |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature Range | TA | -40 | 135 | °C | K range | 2 | |
| Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature Range | Tstg | -55 | 150 | °C | 2 | ||
| Load Supply Voltage | VBB | -40 | V | VBB pin; printed as '- 40 V' | 2 | ||
| Analog Output | V5A | -1 | 45 | V | V5A pin | 2 | |
| Logic Input Signal ENBAT | VENBAT | -0.3 | 45 | V | ENBAT pin input | 2 | |
| Logic Input Signal ENB | VENB | -0.3 | 6.5 | V | ENB pin input | 2 | |
| LX Voltage | VLX | -2 | V | LX pin; upper limit is VBB | 2 | ||
| Thermal resistance junction to ambient | RθJA | 35 | °C/W | 4-layer board, JEDEC high-conductance PCB | 2 | ||
| Input supply range | VBB | 6 | 45 | V | Electrical characteristics range, VENB = 5 V | 4 | |
| Regulated Output Voltage | VREG | 5.5 | 5.8 | V | ILOAD = 550 mA; VBB > 6.5 V | 4 | |
| Dropout Regulated Output Voltage | VREG | 5 | 5.8 | V | Dropout: 6 V ≤ VBB < 6.5 V | 4 | |
| Buck Switch Current Limit | IDSLIM | 1 | 1.2 | 2.2 | A | 4 | |
| Buck Switch On-Resistance | RDSON | 415 | 500 | mΩ | TJ = 25°C | 4 | |
| Buck Switch On-Resistance | RDSON | 650 | 750 | mΩ | TJ = 135°C | 4 | |
| Soft Start Time | tSS | 5 | 10 | 15 | ms | VBB = 14 V | 4 |
| Supply Quiescent Current, enabled | IBB | 6 | 10 | mA | Enabled mode: VENBAT or VENB = HIGH, IOUT = 0 mA; VBB = 14 V | 4 | |
| Supply Quiescent Current, enabled | IBB | 10 | 15 | mA | Enabled mode: VENBAT or VENB = HIGH, IOUT = 0 mA; VBB = 6 V | 4 | |
| Supply Quiescent Current, disabled | IBB | 10 | µA | Disabled mode: VENBAT and VENB = LOW | 4 | ||
| ENBAT Logic Input Voltage HIGH | VENBAT | 2.7 | 45 | V | HIGH input level | 4 | |
| ENBAT Logic Input Voltage LOW | VENBAT | -0.3 | 0.8 | V | LOW input level | 4 | |
| ENBAT Input Current HIGH | IENBAT | 300 | µA | HIGH input level, VENBAT = 45 V | 4 | ||
| ENBAT Input Current HIGH | IENBAT | 70 | µA | HIGH input level, VENBAT = 14 V | 4 | ||
| ENBAT Input Current LOW | IENBAT | -1 | 10 | µA | LOW input level, VENBAT = 0.8 V | 4 | |
| ENB Logic Input Voltage HIGH | VENB | 2.7 | 6.5 | V | HIGH input level | 4 | |
| ENB Logic Input Voltage LOW | VENB | -0.3 | 0.8 | V | LOW input level | 4 | |
| ENB Input Current HIGH | IENB | 50 | µA | HIGH input level, VENB ≥ 2.7 V | 4 | ||
| ENB Input Current LOW | IENB | -1 | 10 | µA | LOW input level, VENB ≤ 0.8 V | 4 | |
| V5D Output Voltage | VOUTV5D | 4.9 | 5 | 5.1 | V | 1 mA ≤ ILOADV5D ≤ 200 mA | 4 |
| V5A Output Voltage | VOUTV5A | 4.9 | 5 | 5.1 | V | 1 mA ≤ ILOADV5A ≤ 200 mA | 4 |
| V33 Output Voltage | VOUTV33 | 3.234 | 3.3 | 3.366 | V | 4 | |
| V5A to V5D Tracking | VTRACK | -25 | 25 | mV | 50 mA ≤ ILOADV5A, ILOADV5D ≤ 200 mA; VBB > 6.5 V | 4 | |
| V5D Current Limit | IOUTV5DLIM | 200 | 300 | mA | 4 | ||
| V5A Current Limit | IOUTV5ALIM | 200 | 300 | mA | 4 | ||
| Base Drive Output Current | IBD | 5 | 10 | 16 | mA | 1 V ≤ VOUTVADJ, VOUTV33 ≤ 4 V | 4 |
| Feedback Voltage | VFB | 1.16 | 1.2 | 1.24 | V | 4 | |
| Feedback Input Bias Current | IFB | -400 | -100 | 100 | nA | 4 | |
| NFAULT, NPOR Output Voltage | VERRON | 400 | mV | Fault asserted; INFAULT, INPOR = 1 mA | 5 | ||
| NFAULT, NPOR Leakage Current | IERROFF | 1 | µA | VNFAULT, VNPOR = 5 V | 5 | ||
| POR Delay | tPOR | 65 | 100 | 135 | ms | C9 = 0.47 µF | 5 |
| V33 Undervoltage Threshold rising | VUVLOV33 | 2.8 | 2.95 | 3.1 | V | V33 rising | 5 |
| V33 Undervoltage Threshold falling | VUVLOV33 | 2.75 | 2.9 | 3.05 | V | V33 falling | 5 |
| V5A, V5D Undervoltage Threshold rising | VUVLOV5 | 4.36 | 4.5 | 4.75 | V | V5A, V5D rising | 5 |
| V5A, V5D Undervoltage Threshold falling | VUVLOV5 | 4.24 | 4.38 | 4.63 | V | V5A, V5D falling | 5 |
| VADJ Undervoltage Threshold rising | VUVLOVADJ | 1.02 | 1.07 | 1.12 | V | VFB rising | 5 |
| VADJ Undervoltage Threshold falling | VUVLOVADJ | 0.97 | 1.02 | 1.07 | V | VFB falling | 5 |
| VADJ, V33 Overcurrent Threshold | VOC | 175 | 200 | 225 | mV | 5 | |
| VREG Undervoltage Threshold | VUVLOVREG | 4.94 | 5.15 | 5.36 | V | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | board (see chart on p. 5). The lead (Pb) free version has 100% matte tin leadframe plating. | 2 |
CAD (KiCad official)
- Symbol:
A8450KLBTR-T - Footprint:
Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm - 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
- 3D model files:
a8450klbtr-t-etched.step/a8450klbtr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a8450klbtr-t.step/a8450klbtr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (17 pp, sha256
e189a1ed6c573955, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# A8450KLBTR-T
**Allegro MicroSystems, LLC** · AC-DC Controllers & Regulators · SOIC-24-300mil
A8450KLBTR-T from Allegro MicroSystems, LLC, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBB | power_in | Load supply input; the electrical characteristics specify operation from 6 to 45 V with an absolute maximum rating of -40 V. |
| 2 | CP2 | passive | Charge pump capacitor positive side, connected to CP1 through a 0.1 µF ceramic capacitor (C8). |
| 3 | CP1 | passive | Charge pump capacitor negative side, connected to CP2 through a 0.1 µF ceramic capacitor (C8). |
| 4 | VCP | power_out | Charge pump output driving the N-channel buck switch; a 0.1 µF ceramic capacitor (C7) connects between VCP and VBB. |
| 5 | VREG11 | passive | Internal reference pin; the datasheet specifies no external connection for it. |
| 6 | GND | power_in | Power ground; internally fused ground lead for enhanced thermal dissipation. |
| 7 | GND | power_in | Power ground; internally fused ground lead for enhanced thermal dissipation. |
| 8 | ENB | input | Logic-level enable input; HIGH input level 2.7 to 6.5 V, LOW input level -0.3 to 0.8 V. |
| 9 | CPOR | passive | POR delay adjustment pin; external capacitor C9 sets tPOR using tPOR = 2.13×105 × CCPOR (ms, µF). |
| 10 | CLADJ | passive | Current limit pin for the adjustable regulator; it should be shorted to VREG if current limiting is not needed. |
| 11 | VADJBD | output | Base drive output for the adjustable regulator pass transistor, with base drive current of 5.0 to 16.0 mA. |
| 12 | FB | input | Feedback input for the adjustable regulator; feedback voltage VFB is 1.16 to 1.24 V. |
| 13 | V5A | power_out | 5 V analog regulator output of 200 mA, protected against short to supply; output voltage 4.9 to 5.1 V. |
| 14 | NPOR | output | Open-drain power-on-reset output that signals a POR event, with output voltage at most 400 mV when asserted. |
| 15 | NFAULT | output | Open-drain diagnostic output, pulled low during fault conditions. |
| 16 | V5D | power_out | 5 V digital regulator output of 200 mA; output voltage 4.9 to 5.1 V. |
| 17 | VREG | power_out | DC-to-DC converter output that supplies the linear regulators; regulated output voltage is 5.50 to 5.80 V. |
| 18 | GND | power_in | Power ground; internally fused ground lead for enhanced thermal dissipation. |
| 19 | GND | power_in | Power ground; internally fused ground lead for enhanced thermal dissipation. |
| 20 | CL33 | passive | Current limit pin for the 3.3 V regulator, set by resistor R3; it should be shorted to VREG if current limiting is not needed. |
| 21 | V33BD | output | Base drive output for the 3.3 V regulator pass transistor. |
| 22 | V33 | power_out | 3.3 V linear regulator output; output voltage 3.234 to 3.366 V. |
| 23 | ENBAT | input | High-voltage enable input; HIGH input level 2.7 to 45 V, LOW input level -0.3 to 0.8 V. |
| 24 | LX | output | Buck converter switching regulator output; LX voltage is rated -2 V to VBB. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-24-300mil |
| Category | Power Supply Chip |
| Pins | 24 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature Range | TA | -40 | | 135 | °C | K range | 2 |
| Junction Temperature | TJ(max) | | | 150 | °C | | 2 |
| Storage Temperature Range | Tstg | -55 | | 150 | °C | | 2 |
| Load Supply Voltage | VBB | -40 | | | V | VBB pin; printed as '- 40 V' | 2 |
| Analog Output | V5A | -1 | | 45 | V | V5A pin | 2 |
| Logic Input Signal ENBAT | VENBAT | -0.3 | | 45 | V | ENBAT pin input | 2 |
| Logic Input Signal ENB | VENB | -0.3 | | 6.5 | V | ENB pin input | 2 |
| LX Voltage | VLX | -2 | | | V | LX pin; upper limit is VBB | 2 |
| Thermal resistance junction to ambient | RθJA | | 35 | | °C/W | 4-layer board, JEDEC high-conductance PCB | 2 |
| Input supply range | VBB | 6 | | 45 | V | Electrical characteristics range, VENB = 5 V | 4 |
| Regulated Output Voltage | VREG | 5.5 | | 5.8 | V | ILOAD = 550 mA; VBB > 6.5 V | 4 |
| Dropout Regulated Output Voltage | VREG | 5 | | 5.8 | V | Dropout: 6 V ≤ VBB < 6.5 V | 4 |
| Buck Switch Current Limit | IDSLIM | 1 | 1.2 | 2.2 | A | | 4 |
| Buck Switch On-Resistance | RDSON | | 415 | 500 | mΩ | TJ = 25°C | 4 |
| Buck Switch On-Resistance | RDSON | | 650 | 750 | mΩ | TJ = 135°C | 4 |
| Soft Start Time | tSS | 5 | 10 | 15 | ms | VBB = 14 V | 4 |
| Supply Quiescent Current, enabled | IBB | | 6 | 10 | mA | Enabled mode: VENBAT or VENB = HIGH, IOUT = 0 mA; VBB = 14 V | 4 |
| Supply Quiescent Current, enabled | IBB | | 10 | 15 | mA | Enabled mode: VENBAT or VENB = HIGH, IOUT = 0 mA; VBB = 6 V | 4 |
| Supply Quiescent Current, disabled | IBB | | | 10 | µA | Disabled mode: VENBAT and VENB = LOW | 4 |
| ENBAT Logic Input Voltage HIGH | VENBAT | 2.7 | | 45 | V | HIGH input level | 4 |
| ENBAT Logic Input Voltage LOW | VENBAT | -0.3 | | 0.8 | V | LOW input level | 4 |
| ENBAT Input Current HIGH | IENBAT | | | 300 | µA | HIGH input level, VENBAT = 45 V | 4 |
| ENBAT Input Current HIGH | IENBAT | | | 70 | µA | HIGH input level, VENBAT = 14 V | 4 |
| ENBAT Input Current LOW | IENBAT | -1 | | 10 | µA | LOW input level, VENBAT = 0.8 V | 4 |
| ENB Logic Input Voltage HIGH | VENB | 2.7 | | 6.5 | V | HIGH input level | 4 |
| ENB Logic Input Voltage LOW | VENB | -0.3 | | 0.8 | V | LOW input level | 4 |
| ENB Input Current HIGH | IENB | | | 50 | µA | HIGH input level, VENB ≥ 2.7 V | 4 |
| ENB Input Current LOW | IENB | -1 | | 10 | µA | LOW input level, VENB ≤ 0.8 V | 4 |
| V5D Output Voltage | VOUTV5D | 4.9 | 5 | 5.1 | V | 1 mA ≤ ILOADV5D ≤ 200 mA | 4 |
| V5A Output Voltage | VOUTV5A | 4.9 | 5 | 5.1 | V | 1 mA ≤ ILOADV5A ≤ 200 mA | 4 |
| V33 Output Voltage | VOUTV33 | 3.234 | 3.3 | 3.366 | V | | 4 |
| V5A to V5D Tracking | VTRACK | -25 | | 25 | mV | 50 mA ≤ ILOADV5A, ILOADV5D ≤ 200 mA; VBB > 6.5 V | 4 |
| V5D Current Limit | IOUTV5DLIM | 200 | 300 | | mA | | 4 |
| V5A Current Limit | IOUTV5ALIM | 200 | 300 | | mA | | 4 |
| Base Drive Output Current | IBD | 5 | 10 | 16 | mA | 1 V ≤ VOUTVADJ, VOUTV33 ≤ 4 V | 4 |
| Feedback Voltage | VFB | 1.16 | 1.2 | 1.24 | V | | 4 |
| Feedback Input Bias Current | IFB | -400 | -100 | 100 | nA | | 4 |
| NFAULT, NPOR Output Voltage | VERRON | | | 400 | mV | Fault asserted; INFAULT, INPOR = 1 mA | 5 |
| NFAULT, NPOR Leakage Current | IERROFF | | | 1 | µA | VNFAULT, VNPOR = 5 V | 5 |
| POR Delay | tPOR | 65 | 100 | 135 | ms | C9 = 0.47 µF | 5 |
| V33 Undervoltage Threshold rising | VUVLOV33 | 2.8 | 2.95 | 3.1 | V | V33 rising | 5 |
| V33 Undervoltage Threshold falling | VUVLOV33 | 2.75 | 2.9 | 3.05 | V | V33 falling | 5 |
| V5A, V5D Undervoltage Threshold rising | VUVLOV5 | 4.36 | 4.5 | 4.75 | V | V5A, V5D rising | 5 |
| V5A, V5D Undervoltage Threshold falling | VUVLOV5 | 4.24 | 4.38 | 4.63 | V | V5A, V5D falling | 5 |
| VADJ Undervoltage Threshold rising | VUVLOVADJ | 1.02 | 1.07 | 1.12 | V | VFB rising | 5 |
| VADJ Undervoltage Threshold falling | VUVLOVADJ | 0.97 | 1.02 | 1.07 | V | VFB falling | 5 |
| VADJ, V33 Overcurrent Threshold | VOC | 175 | 200 | 225 | mV | | 5 |
| VREG Undervoltage Threshold | VUVLOVREG | 4.94 | 5.15 | 5.36 | V | | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | board (see chart on p. 5). The lead (Pb) free version has 100% matte tin leadframe plating. | 2 |
## CAD (KiCad official)
- Symbol: `A8450KLBTR-T`
- Footprint: `Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm`
- 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
- 3D model files: `a8450klbtr-t-etched.step` / `a8450klbtr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a8450klbtr-t.step` / `a8450klbtr-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a8450klbtr-t-datasheet.pdf) (17 pp, sha256 `e189a1ed6c573955`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/a8450klbtr-t-datasheet.pdf)