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Allegro MicroSystems, LLC LED Drivers, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A80601KESJSR-1

Allegro MicroSystems, LLC · LED Drivers · QFN-24-EP(4x4)

A80601KESJSR-1 from Allegro MicroSystems, LLC, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	FAULT	output	Open-drain output pulled low when a fault occurs, requiring a pull-up resistor to the desired logic-level voltage.
2	VDD	power_out	Output of the internal LDO bias regulator, regulated at about 4.25 V, with a 1 µF decoupling capacitor to AGND.
3	AGND	power_in	LED current ground that also serves as the quiet ground for analog signals.
4	COMP	passive	Output of the error amplifier and compensation node, with a series RZ-CZ network from this pin to AGND for loop compensation.
5	ISET	passive	Resistor RISET connected between this pin and AGND sets the 100% LED current.
6	PEB	passive	Pre-Emptive Boost control, where a resistor to AGND fine-tunes the delay between boost switch and LED sinks, and leaving the pin open gives a minimum delay of 1 µs.
7	DITH	passive	Dithering control, where a capacitor to AGND sets the modulation frequency (1 to 22 kHz) and a resistor to FSET sets the range (such as ±5% of fSW).
8	FSET	input	Frequency and synchronization pin, where RFSET to AGND sets fSW from 200 kHz to 2.3 MHz, or an external clock from 260 kHz to 2.3 MHz synchronizes it with dithering disabled.
9	ADIM	input	Analog dimming input accepting a 40 to 1000 kHz PWM clock or a DC level of 0.2 to 2 V for 10% to 100% current, and pulled above 2 V for 100% if unused.
10	PWM	input	Controls the on/off state of the LED current sinks for PWM dimming, typically at 200 Hz to 2 kHz, and may be tied to EN for single-wire dimming.
11	EN	input	Enables the IC when pulled high; when taken low the IC stays in standby for up to 16 ms before full shutdown.
12	CLKOUT	output	Logic output representing the boost oscillator switching frequency, active as long as the IC is enabled, for synchronizing other converters.
13	LED4	passive	LED current sink #4, where the cathode of the LED string connects and an unused pin must be terminated to AGND through 2.37 kΩ.
14	LED3	passive	LED current sink #3, where the cathode of the LED string connects and an unused pin must be terminated to AGND through 2.37 kΩ.
15	LED2	passive	LED current sink #2, where the cathode of the LED string connects and an unused pin must be terminated to AGND through 2.37 kΩ.
16	LED1	passive	LED current sink #1, where the cathode of the LED string connects and an unused pin must be terminated to AGND through 2.37 kΩ.
17	OVP	input	Overvoltage protection input, where an external resistor from VOUT sets the overvoltage protection threshold.
18	PGND	power_in	Power ground for the internal gate driver, to be connected to external power GND by the shortest path.
19	VDRV	power_out	Gate driver supply of about 6.5 V, which requires a 2.2 µF MLCC to PGND for buffering.
20	CS	input	Current sense for peak current control of the power switch, connected to the sense resistor at the source of the external power MOSFET.
21	GDRV	output	Gate driver for the external power switch, connected to the MOSFET gate, which must be fully enhanced at VGS = 5 V.
22	GATE	output	Gate driver output for the external P-channel MOSFET used as the input disconnect switch.
23	VSENSE	input	Negative sense side of the input current sense resistor RSC, with the trip threshold measured as VIN minus VSENSE and a fixed iADJ current sink for adjustment.
24	VIN	power_in	Input power to the IC and the positive side of the input current sense resistor, with an operating input range of 4.5 to 40 V.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	QFN-24-EP(4x4)
Category	Display Modules / LED Drivers / Display Drivers
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
LEDx Pin Voltage	VLEDx	-0.3		40	V	x = 1..4	2
OVP Pin Voltage	VOVP	-0.3		40	V		2
Input Voltage	VIN	-0.3		40	V		2
Gate Driver Supply Voltage	VDRV, VGDRV	-1		7.5	V	VDRV, GDRV pins	2
Current Sense Pin Voltage	VCS	-0.3		7	V		2
Logic and Control Input Voltage		-0.3		5.5	V	EN, PWM, FAULT, ADIM, CLKOUT, COMP, DITH, PEB, FSET, ISET, VDD; external input signals must not be higher than VIN + 0.4 V	2
Operating Ambient Temperature	TA	-40		125	°C	Range K	2
Maximum Junction Temperature	TJ(max)			150	°C		2
Storage Temperature	Tstg	-55		150	°C		2
Operating Input Voltage Range	VIN	4.5		40	V		6
VIN UVLO Start Threshold	VUVLO(rise)			4.45	V	VIN rising	6
VIN UVLO Stop Threshold	VUVLO(fall)			4.05	V	VIN falling	6
UVLO Hysteresis	VUVLO_HYS	300	400	500	mV		6
VIN Pin Operating Current	IOP		22	32	mA	EN and PWM = H, CGATE = 1 nF from GDRV to PGND, fSW = 2 MHz	6
VIN Pin Quiescent Current	IQ		4	6	mA	EN = H and PWM = L, fCLKOUT = 2 MHz	6
VIN Pin Sleep Current	ISLEEP		1	5	µA	VIN = 16 V, VEN / VPWM = VSYNC = 0 V	6
Input Logic Level-Low	VIL			0.4	V		6
Input Logic Level-High	VIH	1.5			V		6
Input Pull-Down Resistor (EN, PWM)	REN, RPWM	60	100	140	kΩ	Input = 5 V	6
Input Pull-Down Resistor (ADIM)	RADIM	30	50	70	kΩ	Input = 5 V	6
Output Logic Level-Low	VOL			0.3	V	5 V < VIN < 40 V, iLOAD = 1 mA	6
Output Logic Level-High	VOH	1.8			V	5 V < VIN < 40 V, iLOAD = 1 mA	6
CLKOUT Duty Cycle	DCLKOUT	33	50	67	%	fSW = 2 MHz, no external sync	6
Analog Dimming Current Level (0.5 V on ADIM)	iADIM25	23	25	27	%	DC 0.5 V applied to ADIM pin	6
APWM Frequency Range	fAPWM	40		1000	kHz	Clock signal applied to ADIM pin	6
APWM Duty Cycle Range	DAPWM	0		90	%	Clock signal applied to ADIM pin	6
VDD Regulator Output Voltage	VDD	4.05	4.25	4.45	V	VIN > 6 V, iLOAD < 1 mA	6
OVP Pin Voltage Threshold	VOVP(th)	2.2	2.5	2.8	V	OVP pin connected to VOUT	7
OVP Pin Sense Current Threshold	iOVP(th)	140	146.5	153	µA	Current into OVP pin at 125ºC	7
OVP Pin Sense Current Threshold (over temperature)	iOVP(th)	140	150	160	µA	Measured over temperature	7
OVP Variation at Output (first limit)	ΔOVP			4	%	Measured at VOUT when ROVP = 188 kΩ	7
OVP Variation at Output (second limit)	ΔOVP			7	%		7
Undervoltage Detection Threshold	VUVP(th)	2.4	2.55	2.7	V	Measured at VOUT when ROVP = 188 kΩ	7
Undervoltage Detection Threshold (ROVP = 0 Ω)	VUVP(th)	0.13	0.2	0.25	V	Measured at VOUT when ROVP = 0 Ω	7
Gate Driver Minimum On-Time	tSW(ON)			100	ns		7
Gate Driver Minimum Off-Time	tSW(OFF)			100	ns		7
Primary Current Sense Limit	iCS(LIM1)	175	210	245	mV	Exceeding iCS(LIM1) causes gate driver to truncate existing cycle, but does not shut down	7
Oscillator Frequency	fSW	1.95	2.15	2.35	MHz	RFSET = 10 kΩ	7
Sync Input Logic Low	VSYNCL			0.4	V	FSET/SYNC pin logic Low	7
Sync Input Logic High	VSYNCH	1.5			V	FSET/SYNC pin logic High	7
Synchronized PWM Frequency	fSWSYNC	260		2300	kHz		7
Synchronization Input Min Off-Time	tPWSYNCOFF	150			ns		7
Synchronization Input Min On-Time	tPWSYNCON	150			ns		7
LEDx Accuracy	ErrLED		0.7	3	%	ISET = 120 µA (RISET = 8.33 kΩ)	8
LEDx Matching	ΔLEDx		0.8	2	%	ISET = 120 µA	8
LEDx Regulation Voltage (A80601-1)	VLED	760	860	960	mV	A80601-1 row; measured individually with all other LED pins tied to ≥1 V, ISET = 120 µA, VADIM > 2.1 V	8
IISET to ILEDx Current Gain	AISET	1432	1466	1500	A/A	ISET = 120 µA	8
ISET Pin Voltage	VISET	0.955	0.985	1.015	V	VADIM > 2.1 V	8
Allowable ISET Current	iISET	20		144	µA	VADIM > 2.1 V	8
LED String Partial-Short Detect	VLEDSD	4.9	5.5	6.1	V	Sensed from each LED pin to GND while its current sink is in regulation; all other LED pins tied to 1 V	8
Soft-Start Ramp-Up Time	tSSRU	6.6	8.2	9.8	ms	Maximum time duration before all LED channels come into regulation, or OVP is tripped, whichever comes first	8
Enable Pin Shut Down Delay	tEN(OFF)	10	16	22	ms	EN goes from High to Low; exceeding tEN(OFF) results in IC shutdown	8
Minimum PWM On-Time	tPWMH		0.3	0.4	µs	First and subsequent PWM pulses	8
VSENSE Pin Sink Current	iADJ	16	20	24	µA		8
VSENSE Trip Point	VSENSETRIP	88	98	108	mV	Measured between VIN and VSENSE, RADJ = 0 Ω	8
FAULT Output Pull-Down Voltage	VFAULT			0.5	V	FAULT = 1 mA	8
External FAULT Input High	VFIH	1.5			V	No internal faults	8
Gate Shutdown Delay When Overcurrent Fault Is Tripped	tGATEFAULT			3	µs	VIN, VSENSE = 200 mV; monitored at FAULT pin	8
Thermal Shutdown Threshold	TSD	155	170		°C	Temperature rising	8
Package Thermal Resistance (junction to ambient)	RθJA		37		°C/W	ES package measured on 4-layer PCB based on JEDEC standard	2

CAD (KiCad official)

Symbol: A80601KESJSR-1
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: a80601kesjsr-1-etched.step / a80601kesjsr-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a80601kesjsr-1.step / a80601kesjsr-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (41 pp, sha256 7385a7f901821bc9, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# A80601KESJSR-1

**Allegro MicroSystems, LLC** · LED Drivers · QFN-24-EP(4x4)

A80601KESJSR-1 from Allegro MicroSystems, LLC, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FAULT | output | Open-drain output pulled low when a fault occurs, requiring a pull-up resistor to the desired logic-level voltage. |
| 2 | VDD | power_out | Output of the internal LDO bias regulator, regulated at about 4.25 V, with a 1 µF decoupling capacitor to AGND. |
| 3 | AGND | power_in | LED current ground that also serves as the quiet ground for analog signals. |
| 4 | COMP | passive | Output of the error amplifier and compensation node, with a series RZ-CZ network from this pin to AGND for loop compensation. |
| 5 | ISET | passive | Resistor RISET connected between this pin and AGND sets the 100% LED current. |
| 6 | PEB | passive | Pre-Emptive Boost control, where a resistor to AGND fine-tunes the delay between boost switch and LED sinks, and leaving the pin open gives a minimum delay of 1 µs. |
| 7 | DITH | passive | Dithering control, where a capacitor to AGND sets the modulation frequency (1 to 22 kHz) and a resistor to FSET sets the range (such as ±5% of fSW). |
| 8 | FSET | input | Frequency and synchronization pin, where RFSET to AGND sets fSW from 200 kHz to 2.3 MHz, or an external clock from 260 kHz to 2.3 MHz synchronizes it with dithering disabled. |
| 9 | ADIM | input | Analog dimming input accepting a 40 to 1000 kHz PWM clock or a DC level of 0.2 to 2 V for 10% to 100% current, and pulled above 2 V for 100% if unused. |
| 10 | PWM | input | Controls the on/off state of the LED current sinks for PWM dimming, typically at 200 Hz to 2 kHz, and may be tied to EN for single-wire dimming. |
| 11 | EN | input | Enables the IC when pulled high; when taken low the IC stays in standby for up to 16 ms before full shutdown. |
| 12 | CLKOUT | output | Logic output representing the boost oscillator switching frequency, active as long as the IC is enabled, for synchronizing other converters. |
| 13 | LED4 | passive | LED current sink #4, where the cathode of the LED string connects and an unused pin must be terminated to AGND through 2.37 kΩ. |
| 14 | LED3 | passive | LED current sink #3, where the cathode of the LED string connects and an unused pin must be terminated to AGND through 2.37 kΩ. |
| 15 | LED2 | passive | LED current sink #2, where the cathode of the LED string connects and an unused pin must be terminated to AGND through 2.37 kΩ. |
| 16 | LED1 | passive | LED current sink #1, where the cathode of the LED string connects and an unused pin must be terminated to AGND through 2.37 kΩ. |
| 17 | OVP | input | Overvoltage protection input, where an external resistor from VOUT sets the overvoltage protection threshold. |
| 18 | PGND | power_in | Power ground for the internal gate driver, to be connected to external power GND by the shortest path. |
| 19 | VDRV | power_out | Gate driver supply of about 6.5 V, which requires a 2.2 µF MLCC to PGND for buffering. |
| 20 | CS | input | Current sense for peak current control of the power switch, connected to the sense resistor at the source of the external power MOSFET. |
| 21 | GDRV | output | Gate driver for the external power switch, connected to the MOSFET gate, which must be fully enhanced at VGS = 5 V. |
| 22 | GATE | output | Gate driver output for the external P-channel MOSFET used as the input disconnect switch. |
| 23 | VSENSE | input | Negative sense side of the input current sense resistor RSC, with the trip threshold measured as VIN minus VSENSE and a fixed iADJ current sink for adjustment. |
| 24 | VIN | power_in | Input power to the IC and the positive side of the input current sense resistor, with an operating input range of 4.5 to 40 V. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | QFN-24-EP(4x4) |
| Category | Display Modules / LED Drivers / Display Drivers |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| LEDx Pin Voltage | VLEDx | -0.3 |  | 40 | V | x = 1..4 | 2 |
| OVP Pin Voltage | VOVP | -0.3 |  | 40 | V |  | 2 |
| Input Voltage | VIN | -0.3 |  | 40 | V |  | 2 |
| Gate Driver Supply Voltage | VDRV, VGDRV | -1 |  | 7.5 | V | VDRV, GDRV pins | 2 |
| Current Sense Pin Voltage | VCS | -0.3 |  | 7 | V |  | 2 |
| Logic and Control Input Voltage |  | -0.3 |  | 5.5 | V | EN, PWM, FAULT, ADIM, CLKOUT, COMP, DITH, PEB, FSET, ISET, VDD; external input signals must not be higher than VIN + 0.4 V | 2 |
| Operating Ambient Temperature | TA | -40 |  | 125 | °C | Range K | 2 |
| Maximum Junction Temperature | TJ(max) |  |  | 150 | °C |  | 2 |
| Storage Temperature | Tstg | -55 |  | 150 | °C |  | 2 |
| Operating Input Voltage Range | VIN | 4.5 |  | 40 | V |  | 6 |
| VIN UVLO Start Threshold | VUVLO(rise) |  |  | 4.45 | V | VIN rising | 6 |
| VIN UVLO Stop Threshold | VUVLO(fall) |  |  | 4.05 | V | VIN falling | 6 |
| UVLO Hysteresis | VUVLO_HYS | 300 | 400 | 500 | mV |  | 6 |
| VIN Pin Operating Current | IOP |  | 22 | 32 | mA | EN and PWM = H, CGATE = 1 nF from GDRV to PGND, fSW = 2 MHz | 6 |
| VIN Pin Quiescent Current | IQ |  | 4 | 6 | mA | EN = H and PWM = L, fCLKOUT = 2 MHz | 6 |
| VIN Pin Sleep Current | ISLEEP |  | 1 | 5 | µA | VIN = 16 V, VEN / VPWM = VSYNC = 0 V | 6 |
| Input Logic Level-Low | VIL |  |  | 0.4 | V |  | 6 |
| Input Logic Level-High | VIH | 1.5 |  |  | V |  | 6 |
| Input Pull-Down Resistor (EN, PWM) | REN, RPWM | 60 | 100 | 140 | kΩ | Input = 5 V | 6 |
| Input Pull-Down Resistor (ADIM) | RADIM | 30 | 50 | 70 | kΩ | Input = 5 V | 6 |
| Output Logic Level-Low | VOL |  |  | 0.3 | V | 5 V < VIN < 40 V, iLOAD = 1 mA | 6 |
| Output Logic Level-High | VOH | 1.8 |  |  | V | 5 V < VIN < 40 V, iLOAD = 1 mA | 6 |
| CLKOUT Duty Cycle | DCLKOUT | 33 | 50 | 67 | % | fSW = 2 MHz, no external sync | 6 |
| Analog Dimming Current Level (0.5 V on ADIM) | iADIM25 | 23 | 25 | 27 | % | DC 0.5 V applied to ADIM pin | 6 |
| APWM Frequency Range | fAPWM | 40 |  | 1000 | kHz | Clock signal applied to ADIM pin | 6 |
| APWM Duty Cycle Range | DAPWM | 0 |  | 90 | % | Clock signal applied to ADIM pin | 6 |
| VDD Regulator Output Voltage | VDD | 4.05 | 4.25 | 4.45 | V | VIN > 6 V, iLOAD < 1 mA | 6 |
| OVP Pin Voltage Threshold | VOVP(th) | 2.2 | 2.5 | 2.8 | V | OVP pin connected to VOUT | 7 |
| OVP Pin Sense Current Threshold | iOVP(th) | 140 | 146.5 | 153 | µA | Current into OVP pin at 125ºC | 7 |
| OVP Pin Sense Current Threshold (over temperature) | iOVP(th) | 140 | 150 | 160 | µA | Measured over temperature | 7 |
| OVP Variation at Output (first limit) | ΔOVP |  |  | 4 | % | Measured at VOUT when ROVP = 188 kΩ | 7 |
| OVP Variation at Output (second limit) | ΔOVP |  |  | 7 | % |  | 7 |
| Undervoltage Detection Threshold | VUVP(th) | 2.4 | 2.55 | 2.7 | V | Measured at VOUT when ROVP = 188 kΩ | 7 |
| Undervoltage Detection Threshold (ROVP = 0 Ω) | VUVP(th) | 0.13 | 0.2 | 0.25 | V | Measured at VOUT when ROVP = 0 Ω | 7 |
| Gate Driver Minimum On-Time | tSW(ON) |  |  | 100 | ns |  | 7 |
| Gate Driver Minimum Off-Time | tSW(OFF) |  |  | 100 | ns |  | 7 |
| Primary Current Sense Limit | iCS(LIM1) | 175 | 210 | 245 | mV | Exceeding iCS(LIM1) causes gate driver to truncate existing cycle, but does not shut down | 7 |
| Oscillator Frequency | fSW | 1.95 | 2.15 | 2.35 | MHz | RFSET = 10 kΩ | 7 |
| Sync Input Logic Low | VSYNCL |  |  | 0.4 | V | FSET/SYNC pin logic Low | 7 |
| Sync Input Logic High | VSYNCH | 1.5 |  |  | V | FSET/SYNC pin logic High | 7 |
| Synchronized PWM Frequency | fSWSYNC | 260 |  | 2300 | kHz |  | 7 |
| Synchronization Input Min Off-Time | tPWSYNCOFF | 150 |  |  | ns |  | 7 |
| Synchronization Input Min On-Time | tPWSYNCON | 150 |  |  | ns |  | 7 |
| LEDx Accuracy | ErrLED |  | 0.7 | 3 | % | ISET = 120 µA (RISET = 8.33 kΩ) | 8 |
| LEDx Matching | ΔLEDx |  | 0.8 | 2 | % | ISET = 120 µA | 8 |
| LEDx Regulation Voltage (A80601-1) | VLED | 760 | 860 | 960 | mV | A80601-1 row; measured individually with all other LED pins tied to ≥1 V, ISET = 120 µA, VADIM > 2.1 V | 8 |
| IISET to ILEDx Current Gain | AISET | 1432 | 1466 | 1500 | A/A | ISET = 120 µA | 8 |
| ISET Pin Voltage | VISET | 0.955 | 0.985 | 1.015 | V | VADIM > 2.1 V | 8 |
| Allowable ISET Current | iISET | 20 |  | 144 | µA | VADIM > 2.1 V | 8 |
| LED String Partial-Short Detect | VLEDSD | 4.9 | 5.5 | 6.1 | V | Sensed from each LED pin to GND while its current sink is in regulation; all other LED pins tied to 1 V | 8 |
| Soft-Start Ramp-Up Time | tSSRU | 6.6 | 8.2 | 9.8 | ms | Maximum time duration before all LED channels come into regulation, or OVP is tripped, whichever comes first | 8 |
| Enable Pin Shut Down Delay | tEN(OFF) | 10 | 16 | 22 | ms | EN goes from High to Low; exceeding tEN(OFF) results in IC shutdown | 8 |
| Minimum PWM On-Time | tPWMH |  | 0.3 | 0.4 | µs | First and subsequent PWM pulses | 8 |
| VSENSE Pin Sink Current | iADJ | 16 | 20 | 24 | µA |  | 8 |
| VSENSE Trip Point | VSENSETRIP | 88 | 98 | 108 | mV | Measured between VIN and VSENSE, RADJ = 0 Ω | 8 |
| FAULT Output Pull-Down Voltage | VFAULT |  |  | 0.5 | V | FAULT = 1 mA | 8 |
| External FAULT Input High | VFIH | 1.5 |  |  | V | No internal faults | 8 |
| Gate Shutdown Delay When Overcurrent Fault Is Tripped | tGATEFAULT |  |  | 3 | µs | VIN, VSENSE = 200 mV; monitored at FAULT pin | 8 |
| Thermal Shutdown Threshold | TSD | 155 | 170 |  | °C | Temperature rising | 8 |
| Package Thermal Resistance (junction to ambient) | RθJA |  | 37 |  | °C/W | ES package measured on 4-layer PCB based on JEDEC standard | 2 |

## CAD (KiCad official)

- Symbol: `A80601KESJSR-1`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `a80601kesjsr-1-etched.step` / `a80601kesjsr-1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a80601kesjsr-1.step` / `a80601kesjsr-1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a80601kesjsr-1-datasheet.pdf) (41 pp, sha256 `7385a7f901821bc9`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/a80601kesjsr-1-datasheet.pdf)

A80601KESJSR-1

Verified A80601KESJSR-1

Verification log 1 record

A80601KESJSR-1

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance