component
A6986F5VTR
Public Made by Adomby adom
STMicroelectronics DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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A6986F5VTR
STMicroelectronics · DC-DC Converters · HTSSOP-16-EP
A6986F5VTR from STMicroelectronics, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RST | output | The RST open collector output is driven low when the output voltage is out of regulation and is released after an adjustable DELAY time once the output voltage is over the active delay threshold. |
| 2 | VCC | power_out | Connect a ceramic capacitor (≥ 470 nF) to filter the internal voltage reference; this pin supplies the embedded analog circuitry. |
| 3 | SS/INH | passive | An open collector stage can disable the device by clamping this pin to GND (INH mode), and an internal current generator (4 A typ.) charges the external capacitor to implement the soft-start. |
| 4 | SYNCH/ISKP | input | This pin selects Master/Slave synchronization in LNM and skip current level in LCM, and in LNM it should be left floating when not used. |
| 5 | FSW | input | A pull-up resistor (E24 series only) to VCC or pull-down to GND selects the switching frequency, with pinstrapping active only before the soft-start phase. |
| 6 | MLF | input | A pull-up resistor (E24 series only) to VCC or pull-down to GND selects the low noise mode/low consumption mode and the active RST threshold, with pinstrapping active only before the soft-start phase. |
| 7 | COMP | output | This is the output of the error amplifier, to which the designed compensation network is connected. |
| 8 | DELAY | passive | An external capacitor connected at this pin sets the time DELAY to assert the rising edge of the RST open collector output after the output voltage is over the reset threshold; if left floating, RST acts like a Power Good. |
| 9 | VOUT | input | This pin is the output voltage sensing input. |
| 10 | SGND | power_in | This is the signal GND and must be connected to the exposed pad. |
| 11 | PGND | power_in | This is a power GND pin and must be connected to the exposed pad. |
| 12 | PGND | power_in | This is a power GND pin and must be connected to the exposed pad. |
| 13 | LX | output | This is the switching node, with absolute maximum voltage of -0.3 V to VIN + 0.3 V. |
| 14 | LX | output | This is the switching node, with absolute maximum voltage of -0.3 V to VIN + 0.3 V. |
| 15 | VIN | power_in | This is the DC input voltage pin, with an operating input voltage range of 4 V to 38 V. |
| 16 | VBIAS | power_in | This pin is typically connected to the regulated output voltage to supply part of the analog circuitry for better light-load efficiency, and it should be connected to GND if not used. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | HTSSOP-16-EP |
| Category | Power Management ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating input voltage range | VIN | 4 | 38 | V | 8 | ||
| VCC UVLO rising threshold | VINH | 2.7 | 3.5 | V | 8 | ||
| VCC UVLO falling threshold | VINL | 2.4 | 3.5 | V | 8 | ||
| Peak current limit | IPK | 2.3 | A | Duty cycle < 20% | 8 | ||
| Peak current limit | IPK | 1.8 | A | Duty cycle = 100%, closed loop operation | 8 | ||
| Valley current limit | IVY | 2.4 | A | 8 | |||
| Programmable skip current limit | ISKIPH | 0.2 | 0.4 | 0.6 | A | LCM, VSYNCH = GND | 8 |
| Reverse current limit | IVY_SNK | 0.5 | 1 | 2 | A | LNM or VOUT overvoltage | 8 |
| High-side RDSON | RDSON HS | 0.18 | 0.36 | ISW = 1 A | 8 | ||
| Low-side RDSON | RDSON LS | 0.15 | 0.3 | ISW = 1 A | 8 | ||
| FSW biasing current | IFSW | 0 | 500 | nA | SS ended | 8 | |
| MLF biasing current | IMLF | 0 | 500 | nA | SS ended | 8 | |
| Duty cycle | D | 0 | 100 | % | 8 | ||
| Minimum on time | TON MIN | 80 | ns | 8 | |||
| VCC LDO output voltage | VCC | 2.9 | 3.3 | 3.6 | V | VBIAS = GND (no switchover) | 8 |
| SWO VBIAS threshold, switch supply from VIN to VBIAS | SWO | 2.85 | 3.2 | V | 3 V < VBIAS < 5.5 V | 8 | |
| SWO VBIAS threshold, switch supply from VBIAS to VIN | SWO | 2.78 | 3.15 | V | 3 V < VBIAS < 5.5 V | 8 | |
| Shutdown current from VIN | ISHTDWN | 4 | 8 | 15 | µA | VSS/INH = GND | 9 |
| Quiescent current from VIN, LCM with SWO | IQ OPVIN | 4 | 10 | 15 | µA | LCM - SWO, VREF < VFB < VOVP (SLEEP), VBIAS = 3.3 V | 9 |
| Quiescent current from VIN, LCM without SWO | IQ OPVIN | 35 | 70 | 120 | µA | LCM - NO SWO, VREF < VFB < VOVP (SLEEP), VBIAS = GND | 9 |
| Quiescent current from VIN, LNM with SWO | IQ OPVIN | 0.5 | 1.5 | 5 | mA | LNM - SWO, VFB = GND (NO SLEEP), VBIAS = 3.3 V | 9 |
| Quiescent current from VIN, LNM without SWO | IQ OPVIN | 2 | 2.8 | 6 | mA | LNM - NO SWO, VFB = GND (NO SLEEP), VBIAS = GND | 9 |
| Quiescent current from VBIAS, LCM with SWO | IQ OPVBIAS | 25 | 50 | 115 | µA | LCM - SWO, VREF < VFB < VOVP (SLEEP), VBIAS = 3.3 V | 9 |
| Quiescent current from VBIAS, LNM with SWO | IQ OPVBIAS | 0.5 | 1.2 | 5 | mA | LNM - SWO, VFB = GND (NO SLEEP), VBIAS = 3.3 V | 9 |
| VSS threshold, SS rising | VINH | 200 | 460 | 700 | mV | SS rising | 9 |
| VSS hysteresis | VINH HYST | 100 | 140 | mV | 9 | ||
| CSS charging current | ISS CH | 1 | µA | VSS < VINH OR t < TSS SETUP OR VEA+ > VFB | 9 | ||
| CSS charging current | ISS CH | 4 | µA | t > TSS SETUP AND VEA+ < VFB | 9 | ||
| Start of internal error amplifier ramp | VSS START | 0.995 | 1.1 | 1.15 | V | 9 | |
| VOUT voltage feedback, 5 V variant | VOUT | 4.925 | 5 | 5.075 | V | A6986F5V | 9 |
| VOUT biasing current, 5 V variant | IVOUT | 7.5 | 10 | 13.5 | µA | 5 V (A6986F5V) | 9 |
| Error amplifier gain | AV | 100 | dB | 10 | |||
| Current sense transconductance | gCS | 2.5 | A/V | Ipk = 1 A | 10 | ||
| Slope compensation | VPP*gCS | 0.45 | 0.75 | 1 | A | 10 | |
| Overvoltage trip (VOVP/VREF) | VOVP | 1.15 | 1.2 | 1.25 | 10 | ||
| Overvoltage hysteresis | VOVP HYST | 0.5 | 2 | 5 | % | 10 | |
| Synchronization frequency | fSYN MIN | 266.5 | kHz | LNM; fSW = VCC | 10 | ||
| SYNCH input threshold | VSYN TH | 0.7 | 1.2 | V | LNM, SYNCH rising | 10 | |
| SYNCH pull-down current | ISYN | 0.7 | mA | LNM, VSYN = 1.2 V | 10 | ||
| SYNCH high level output | VSYN OUT | 1.4 | V | LNM, 5 mA sinking load | 10 | ||
| SYNCH low level output | VSYN OUT | 0.6 | V | LNM, 0.7 mA sourcing load | 10 | ||
| RST hysteresis | VTHR HYST | 2 | % | 10 | |||
| RST threshold, 5 V variant, 93% target | VRST | 4.557 | 4.65 | 4.743 | V | LCM, RVCC 0, RGND NC, VRST/VOUT 93% | 12 |
| RST threshold, 5 V variant, 80% target | VRST | 3.92 | 4 | 4.08 | V | LCM, RVCC 8.2 kOhm, RGND NC, VRST/VOUT 80% | 12 |
| RST threshold, 5 V variant, 87% target | VRST | 4.263 | 4.35 | 4.437 | V | LCM, RVCC 18 kOhm, RGND NC, VRST/VOUT 87% | 12 |
| RST threshold, 5 V variant, 96% target | VRST | 4.704 | 4.8 | 4.896 | V | LCM, RVCC 39 kOhm, RGND NC, VRST/VOUT 96% | 12 |
| Selected RST delay threshold | VTHD | 1.19 | 1.234 | 1.258 | V | VFB > VTHR | 10 |
| Thermal shutdown temperature | TSHDWN | 165 | °C | 10 | |||
| Thermal shutdown hysteresis | THYS | 30 | °C | 10 | |||
| Input voltage absolute maximum | VIN | -0.3 | 40 | V | 6 | ||
| VOUT absolute maximum | VOUT | -0.3 | 10 | V | 6 | ||
| Operating junction temperature range | TJ | -40 | 150 | °C | 6 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 6 | ||
| Lead temperature | TLEAD | 260 | °C | soldering 10 sec. | 6 | ||
| High-side / low-side switch current | IHS, ILS | 2 | A | 6 | |||
| Thermal resistance junction to ambient | Rth JA | 40 | °C/W | device soldered on the STMicroelectronics demonstration board | 7 | ||
| Thermal resistance junction to exposed pad | Rth JC | 5 | °C/W | for board design | 7 |
CAD (KiCad official)
- Symbol:
A6986F5VTR - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
a6986f5vtr-etched.step/a6986f5vtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a6986f5vtr.step/a6986f5vtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (79 pp, sha256
45ee66d8f0b77549, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).