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A6727TR

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STMicroelectronics DC-DC Converters, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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A6727TR

STMicroelectronics · DC-DC Converters · SO-8

A6727TR from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT power_in HS driver supply, to be connected through a 100 μF capacitor to the floating node (LS drain) pin with a bootstrap diode provided.
2 UGATE output HS driver output, connected to the high-side MOSFET gate.
3 GND power_in Common reference for all internal references, logic and drivers, to be connected to the PCB ground plane.
4 LGATE output LS driver output, connected to the low-side MOSFET gate.
5 VCC power_in Device and LS driver supply with operative range from 4.1 V to 13.2 V, to be filtered with at least 1 μF MLCC to GND.
6 FB input Error amplifier inverting input, connected to the regulated output through RFB, with optional ROS to GND for voltages above the 0.8 V reference.
7 COMP / DIS / OC bidirectional Error amplifier output (COMP) connected to FB through an RF-CF//CP network; DIS disables the device when forced below 0.5 V (typ.); OC sets the overcurrent threshold through ROCSET connected to VCC only when VCC is 5 V.
8 PHASE passive HS driver return path, current sense and adaptive deadtime monitor, connected to the LS drain to sense the RDS(on) drop for output current measurement.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Device supply voltage VCC 4.1 13.2 V See Figure 1 7
Conversion input voltage VIN 13.2 V 7
Conversion input voltage VIN 19 V VCC < 7.0 V 7
VCC supply current ICC 6 mA UGATE and LGATE = open 7
BOOT supply current IBOOT 0.5 mA UGATE = open; PHASE to GND 7
Main oscillator accuracy FSW 270 300 330 kHz TA = 25 °C 7
Main oscillator accuracy FSW 250 300 350 kHz 7
Maximum duty cycle dMAX 80 % 7
Output voltage accuracy VOUT -1 1 % VOUT = 0.8 V, TA = 25 °C 7
Output voltage accuracy VOUT -1.5 1.5 % VOUT = 0.8 V 7
Input bias current IFB 100 nA Sourced from FB 7
Disable threshold DIS 0.43 0.5 V COMP falling 7
HS source current IUGATE 1.5 A BOOT - PHASE = 5 V to 12 V 7
HS sink resistance RUGATE 1.1 Ω BOOT - PHASE = 5 V to 12 V 7
LS source current ILGATE 1.5 A VCC = 5 V to 12 V 7
LS sink resistance RLGATE 0.65 Ω VCC = 5 V to 12 V 7
OCSET current source IOCSET 55 60 65 μA TA = 25 °C; Sunk from COMP pin, before SS 8
OCSET current source IOCSET 52 60 68 μA 8
OC switch-over threshold VCC_OC 8 V VCC rising 8
Fixed OC threshold VOC_TH -400 mV VPHASE to GND, VCC > VCC_OC 8
OVP threshold OVP 1 V FB rising 8
UVP threshold UVP 0.6 V FB falling 8
Thermal resistance junction-to-ambient Rth(JA) 85 °C/W Mounted on 2S2P board in free air 6
Maximum junction temperature TMAX 150 °C 6
Storage temperature range TSTG -40 150 °C 6
Junction temperature range TJ -40 150 °C 6
VCC to GND VCC -0.3 15 V to GND 6
VBOOT to PHASE VBOOT 15 V to PHASE 6
VBOOT to GND VBOOT 45 V to GND 6
VUGATE to GND VUGATE -0.3 V to GND; max VBOOT + 0.3 6
VUGATE to PHASE VUGATE -0.3 V to PHASE; max (VBOOT - VPHASE) + 0.3 6
VUGATE to PHASE, t < 50 ns VUGATE -1 V to PHASE; t < 50 ns 6
VPHASE to GND VPHASE -8 30 V to GND 6
VLGATE to GND VLGATE -0.3 V to GND; max VCC + 0.3 6
VLGATE to GND, t < 50 ns VLGATE -1 V to GND; t < 50 ns 6
COMP to GND COMP -0.3 7 V to GND 6
FB to GND FB -0.3 3.6 V to GND 6
UVLO VCC turn-on UVLO 4.1 V VCC rising 7
UVLO hysteresis UVLO 0.2 V Hysteresis 7
PWM ramp amplitude DVOSC 1.5 V 7
DC gain A0 120 dB Guaranteed by design, not to be tested 7
Gain-bandwidth product GBWP 15 MHz Guaranteed by design, not to be tested 7
Slew rate SR 8 V/μs Guaranteed by design, not to be tested 7

CAD (KiCad official)

  • Symbol: A6727TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: a6727tr-etched.step / a6727tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a6727tr.step / a6727tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (29 pp, sha256 649dc4b46f5bb570, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF